Microprocessor silicon debug based on failure propagation tracing

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 284-293

  Caty, Olivier ^a   Dahlgren, Peter ^a   Bayraktaroglu, Ismet ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; DATA REDUCTION; FAILURE ANALYSIS; MICROPROCESSOR CHIPS;

FUNCTIONAL FAILURES; SCAN DUMP ANALYSIS; TIME-TO-MARKET (TTM);

SILICON;

EID: 33847169370     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1583986     Document Type: Conference Paper

References (8)

1. Kinra, A., "Towards Reducing Functional Only Fails for the UltraSPARC Microprocessors", Proc. International Test Conference, 1999, pp. 147-154
2. Josephon, D. et al, "Debug Methodology for the McKinley Processor", Proc. International Test Conference, 2001, pp. 451-460
3. Katz, J., "A Case Study in the use of Scan in microSPARC testing and debug", Proc. International Test Conference, 1994, pp. 70-75
4. Goel, S.K. and Vermeulen, B, "Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips", Proc. International Test Conference, 2002, pp. 1103-1110
5. Dahlgren. P et al, "Latch Divergence in Microprocessor Failure Analysis", Proc. International Test Conference, 2003, pp. 755-763
6. Josephon, D., "The Manic Depression of Microprocessor Debug", Proc. International Test Conference, 2002, pp. 657-663
7. Kwon, Y-J. et al, "FakeFault: a Silicon Debug Software Tool for Microprocessors Embedded Memory Arrays", Proc. International Test Conference, 1998, pp. 727-732
8. Ross, D-E. et al, "Conversion of small functional test sets of nonscan blocks to scan patterns", Proc. International Test Conference, 2000, pp. 691-700