Automated debug of speed path failures using functional tests

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2009, Pages 91-96

  McLaughlin, Rich ^a   Venkataraman, Srikanth ^a   Lim, Carlston ^b  

^a INTEL CORPORATION   (United States)

^b Intel Technology Malaysia Sdn Bhd   (Malaysia)

Author keywords

Component; Design for debug; Functional tests; Silicon debug; Speed path; Timing

Indexed keywords

COMPONENT; DESIGN FOR DEBUG; FUNCTIONAL TESTS; SILICON DEBUG; TIMING;

DESIGN; FEATURE EXTRACTION; SPEED; TIME MEASUREMENT;

TESTING;

EID: 70349749366     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2009.53     Document Type: Conference Paper

References (10)

1. G. J. Van Rootselaar and B. Vermeulen, "Silicon debug: scan chains alone are not enough," Proc. Int'l Test Conf., pp. 892-902, Sept. 1999.
2. D. Josephson, S. Poehlman, and V. Govan, "Debug Methodology for the McKinley Processor," Proc. Int'l Test Conf., pp. 451-460, 30 Oct. 1 Nov. 2001.
3. Jeremy A. Rowlette and Travis M. Eiles, "Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA)," Proc. Int'l Test Conf., pp. 264-273.
4. Parvathala, P.; Maneparambil, K.; Lindsay, W., "FRITS - a microprocessor functional BIST method", Proc. Int'l Test Conf., 2002, pp. 590-598.
5. A. Carbine, "Scan Mechanism for Monitoring the State of Internal Signals of a VLSI Microprocessor Chip," U.S. Patent No. 5,253,255. October 12, 1993
6. A. Carbine and D. Feltham, "Pentium Pro Processor Design for Test and Debug," Proc. Int'l Test Conf., pp. 294-303, 1-6 Nov 1997.
7. N. A. Kurd, J. S. Barkarullah, R. O. Dizon, T. D. Fletcher, and P. D. Madland, "A multigigahertz clocking scheme for the Pentium 4 microprocessor," IEEE Journal of Solid-State Circuits, Vol. 36, No. 11, pp. 1647-1653, Nov. 2001.
8. Josephson, D.; Gottlieb, B.; The crazy mixed up world of silicon debug [IC validation]; Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004; 3-6 Oct. 2004 Page(s):665-670
9. R.C. Tekumalla, S. Venkataraman, and J. G. Dastidar, "On Diagnosing Path Delay Faults in an At-Speed Environment", IEEE VLSI Test Symposium, April-May 2001, pp. 28-33.
10. S. Venkataraman, S. Drummonds, "Poirot: Applications of a Logic Fault Diagnosis Tool", IEEE Design & Test of Computers, Jan.-Feb. 2001 pp. 19-31.