Stress memorization technique-fundamental understanding and low-cost integration for advanced CMOS technology using a nonselective process

IEEE Transactions on Electron Devices

Volumn 56, Issue 8, 2009, Pages 1690-1697

  Ortolland, Claude ^a   Okuno, Yasutoshi ^b   Verheyen, Peter ^a   Kerner, Christoph ^a   Stapelmann, Chris ^c,d   Aoulaiche, Marc ^a   Horiguchi, Naoto ^a   Hoffmann, Thomas ^a  

^a IMEC   (Belgium)

^b PANASONIC CORPORATION   (Japan)

^c INFINEON TECHNOLOGIES AG   (Germany)

^d SolarWorld Industries America   (United States)

Author keywords

Fully silicided (FUSI) polysilicon gate; Metal gate metal inserted polysilicon (MIPS) ; Strained silicon; Stress memorization technique (SMT)

Indexed keywords

ADVANCED CMOS; FULLY SILICIDED; FULLY SILICIDED (FUSI) POLYSILICON GATE; LOW-COST SOLUTION; MASK LESS; METAL GATE [METAL INSERTED POLYSILICON (MIPS)]; NMOS DEVICES; POLYSILICON GATES; STRAINED SILICON; STRESS MEMORIZATION TECHNIQUE (SMT); STRESS MEMORIZATION TECHNIQUES;

CMOS INTEGRATED CIRCUITS; METALS; PLASMA WAVES; SILICIDES;

POLYSILICON;

EID: 68349137943     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2024021     Document Type: Article

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