Multiple stress memorization in advanced SOI CMOS technologies

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2007, Pages 216-217

  Wei, A ^a   Wiatr, M ^a   Mowry, A ^a   Gehring, A ^a   Boschke, R ^a   Scott, C ^a   Hoentschel, J ^a   Duenkel, S ^a   Gerhardt, M ^a   Feudel, T ^a   Lenski, M ^a   Wirbeleit, F ^a   Otterbach, R ^a   Callahan, R ^a   Koerner, G ^a   Krumm, N ^a   Greenlaw, D ^a   Raab, M ^a   Horstmann, M ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CRYSTALLINE MATERIALS; FOOD ADDITIVES; SILICON;

CAPPING LAYER (GC LAYER); CRYSTALLINE STATES; DRIVE CURRENTS; HIGH TEMPERATURE (HT); LOW TEMPERATURE (LTR); SILICON-ON-INSULATORS (SOI) CMOS; VLSI TECHNOLOGIES;

TECHNOLOGY;

EID: 40949162000     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2007.4339698     Document Type: Conference Paper

References (6)

1. T. Gahni, et al., IEDM 2003, p. 978
2. M. Horstmann, et al., IEDM 2005, p. 243
3. K. Ota, et al., IEDM 2002, p.27
4. C.H. Chen, et al., VLSI 2004, p. 56
5. T.Y. Chang, et al., SSDM 2005, p. 888
6. Ortolland, et al., VLSI 2006, p. 9