Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology

ESSCIRC 2004 - Proceedings of the 34th European Solid-State Device Research Conference

Volumn , Issue , 2004, Pages 137-140

  Ortolland, C ^a,d   Orain, S ^a   Rosa, J ^b   Morin, P ^b   Arnaud, F ^b   Woo, M ^c   Poncet, A ^d   Stolk, P ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

^b STMICROELECTRONICS   (France)

^c MOTOROLA INC   (United States)

^d INSTITUT DES NANOTECHNOLOGIES DE LYON   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHARACTERIZATION; CHEMICAL VAPOR DEPOSITION; COMPUTER SIMULATION; ETCHING; QUANTUM ELECTRONICS; SUBSTRATES; TRANSISTORS;

CONTACT ETCH STOP LAYERS; ION CURVES; SPIKE ANNEAL; STRAINED LAYERS;

CMOS INTEGRATED CIRCUITS;

EID: 17644403553     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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8. R. Bianchi et al, IEDM Tech. Dig. 2002, pg 117-120
9. C. Gallon et al, ESSDERC 2003, pg 359-362