Design and defect tolerance beyond CMOS

Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

Volumn , Issue , 2008, Pages 223-229

  Hu, Xiaobo Sharon ^a   Khitun, Alexander ^c   Likharev, Konstantin K ^b   Niemier, Michael T ^a   Bao, Mingqiang ^c   Wang, Kang L ^c  

^a University of Notre Dame   (United States)

^b STONY BROOK UNIVERSITY   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS; DEFECTS; FITS AND TOLERANCES; INTEGRATED CIRCUITS; MAGNETIC DOMAINS; TECHNOLOGY; VLSI CIRCUITS;

APPLICATION DOMAINS; BEYOND CMOS; CMOS CHIPS; CMOS CIRCUITS; COMPUTATIONAL MODELS; COMPUTING DEVICES; CRITICAL FACTORS; DEFECT RATES; DEFECT TOLERANCES; FUNCTIONAL REQUIREMENTS; MAGNETIC INTERACTIONS; NANO-SCALE STRUCTURES; NEW OPPORTUNITIES; NON-TRADITIONAL; POTENTIAL APPLICATIONS; STATE REPRESENTATIONS; SYSTEM DESIGNS; UNIQUE FEATURES;

EMBEDDED SYSTEMS;

EID: 63349102812     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1450135.1450187     Document Type: Conference Paper

References (66)

1. International Technology Roadmap for Semiconductors. 2007 Edition. 2007. available online at http://www.itrs.net/Links/2007ITRS/Home2007.htm.
2. H. B. Akkerman et al. Towards molecular electronics with large-area molecular junctions. Nature, 441:69-72, Feb. 2007.
3. I. G. Baek et al. Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage applications. In Tech. Dig. IEDM'05, pages 750-753, 2005.
4. J. Billen et al. Improved CuTCNQ resistive non-volatile memories and a statistical study on their threshold voltage. In Proc. ICMTD'07, pages 135-137, 2007.
5. D. Bratton et al. Recent progress in high resolution lithography. Polymers for Adv. Technol, 17:94-103, Feb. 2006.
6. A. Chen et al. Non-volatile resistive switching for advanced memory applications. In Tech. Dig. IEDM'05, page 31.4, 2005.
7. M. Crocker, X. S. Hu, and M. Niemier. Fault models and yield analysis for QCA-based PLAs. Int. Sym. on FPL, pages 435-140, 2007.
8. G. Csaba, P. Lugli, A. Csurgay, and W. Porod. Simulation of power gain and dissipation in field-coupled nanomagnet. J. of Comp. Elec, 4(1-2), 2005.
9. N. Dao, S. Whittenburg, and R. Cowburn. Micromagnetics simulation of deep-submicron supermalloy disks. J. of Appl. Phys., 90(10):5235-7, 2001.
10. A. DeHon and K. K. Likharev. Hybrid CMOS / nanoelectronic digital circuits. In Proc. ICCAD'05, pages 375-382, 2005.
11. W. R. Dichtel et al. Designing bistable [2]rotaxanes for molecular electronic devices. Phil. Trans. R. Soc. A, 365:1607-1625, 2007.
12. M. Donahue and D. Porter. OOMMF user's guide, version 1.0, interagency report NISTIR 6367. http://math.nist.gov/oommf.
13. A. K. et al. Inductively coupled circuits with spin wave bus for information processing. Journal of Nanoelectronics and Optoelectronics, 3:24-34, 2008.
14. A. K. et al. Logic devices with spin wave buses - an approach to scalable magneto-electric circuitry. Procedings of the Material Research Society, 2008.
15. S. Föiling, Ö. Türel, and K. K. Likharev. Single-electron latching switches as nanoscale synapses. In Proc. IJCNN'01, pages 216-221, 2001.
16. C. J. Gao and D. Hammerstrom. Cortical models onto CMOL and CMOS - Architectures and performance/price. IEEE Trans, on Circ. Syst, 54:2502-2515, Nov. 2007.
17. 11 bits per square centimetre. Nature, 445:414-117, Jan. 2007.
18. I. W. Hamley. Nanostructure fabrication using block copolymers. Nanotechnology, 14:R39-R54, Oct. 2003.
19. J. H. Heath et al. A defect-tolerant computer architecture: Opportunities for nanotechnology. Science, 280:1716-1721, Jun. 1998.
20. A. Imre, G. Csaba, L. Ji, A. Orlov, G. Bernstein, and W. Porod. Majority logic gate for Magnetic Quantum-dot Cellular Automata. Science, 311 no. 5758:205-208, January 13, 2006.
21. S. H. Jo and W. Lu. CMOS compatible nanoscale nonvolatile switching memory. Nano Lett, 8:392-397, Jan. 2008.
22. G.-Y. Jung et al. Circuit fabrication at 17 nm half-pitch by nanoimprint lithography. NanoLett., 6:351-354, Mar. 2006.
23. A. Khitun, M. Bao, and K. Wang. Spin wave magnetic nano-fabric: a new approach to spin-based logic circuitry. IEEE Transactions on Magnetics, 2008.
24. A. Khitun and K. Wang. Nano scale computational architectures with spin wave bus. Superlattices & Microstructures, 38:184-200, 2005.
25. A. Khitun and K. L. Wang. Nano logic circuits with spin wave bus. International Conference on Information Technology: New Generation, page 6, 2006.
26. M. P. Kostylev, A. A. Serga, T. Schneider, B. Leven, and B. Hillebrands. Spin-wave logical gates. Applied Physics Letters, 87:153501-1-3, 2005.
27. M. N. Kozicki. Nanoscale memory elements based on solid-state electrolytes. IEEE Trans, on Nanotechnology, 4:331-338, May 2005.
28. J. H. Lee and K. K. Likharev. Crossnets as pattern classifiers. Lecture Notes in Computer Science, 3512:446-154, 2005.
29. J. H. Lee and K. K. Likharev. In situ training of CMOL CrossNets. In Proc. WCCI/IJCNN'06, pages 5026-5024, 2006.
30. J. H. Lee and K. K. Likharev. Defect-tolerant nanoelectronic pattern classifiers. Int. J. Circ. Theory App., 35:239-4, 2007.
31. J. H. Lee, X. Ma, and K. K. Likharev. CMOL Crossnets: Possible neuromorphic nanoelectronic circuits. In Y. Weiss et al., editor, Advances in Neural Information Processing Systems, volume 18, pages 755-762. MIT Press, 2006.
32. C. Lent and P. Tougaw. A device architecture for computing with quantum dots. Proc. of the IEEE, 85:541, 1997.
33. K. K. Likharev. Electronics below 10 nm. In J. Greer etal., editor, Nano and Giga Challenges in Microelectronics, pages 27-68. Elsevier, Amsterdam, 2003.
34. K. K. Likharev. CMOL: A silicon-based bottom-up approach to nanoelectronics. Interface, 14:43-45, May 2005.
35. K. K. Likharev. CMOL: Freeing advanced lithography from the alignment accuracy burden. J. Vac. Sci. Technol. B, 25:2531-2536, Nov. 2007.
36. K. K. Likharev. Resistive and hybrid CMOS/nanodevice memories. In J. E. Brewer and M. Gill, editors, Nonvolatile Memory Technologies with Emphasis on Flash, pages 696-703. IEEE Press, Hoboken, NJ, 2008.
37. K. K. Likharev and D. B. Strukov. CMOL: Devices, circuits, and architectures. In G. Cuniberti et al., editor, Introducing Molecular Electronics, pages 447-177. Springer, Berlin, 2005.
38. K. K. Likharev and D. B. Strukov. Prospects for the development of digital CMOL circuits. In Proc. NanoArch'07, pages 109-116, 2007.
39. K. K. Likharev et al. CrossNets - High-performance neuromorphic architectures for CMOL circuits. Ann. NY Acad. Sci., 1006:15-58, 2003.
40. A. K. M. M. Eshaghian-Wilner, S. Navab and K. L. Wang. Constant-time image processing on spin-wave nano-architectures. Physica Status Solidi, 2007.
41. X. Ma and K. K. Likharev. Global reinforcement learning in stochastic neural networks. IEEE Trans. on Neural Networks, 18:573-577, Mar. 2007.
42. M. Masssoumi et al. Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal-oxide- semiconductor-molecular circuits. Nanotechnology, 17:89-99, Jan. 2005.
43. A. Mayr et al. Synthesis of oligo(phenyleneethynylene)s containing central pyromellitdiimide or naphthalenediimide groups and bearing terminal isocyanide groups: molecular components for single-electron transistors. Tetrahedron, 63:8206-8217, Aug. 2007.
44. G. I. Meijer. Who wins the nonvolatile memory race? Science, 319:1625-1626, Mar. 2008.
45. A. R. Meo. Majority gate networks. IEEE Transactions on Electronic Computers, EC-15:606-18, 1966.
46. M. Niemier, M. Alam, X. S. Hu, G. Bernstein, W. Porod, M. Putney, and J. DeAngelis. Clocking structures and power analysis for nanomagnet-based logic devices. ISLPED, pages 26-31, 2007.
47. M. Niemier, M. Crocker, and X. Hu. Fabrication variations and defect tolerance for nanomagnet-based QCA. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Sys., Oct. 1-3, 2008.
48. G. A. Prinz. Magnetoelectronics. Science, 282:1660-63, 1998.
49. T. Roska. Analogic wave computers-wave-type algorithms: canonical description, computer classes, and computational complexity. IEEE International Symposium on Circuits and Systems, 2:41-4, 2001.
50. T. Schneider, A. A. Serga, B. Leven, B. Hillebrands, R. L. Stamps, and M. P. Kostylev. Realization of spin-wave logic gates. Appl. Phys. Lett., 92:022505-3, 2008.
51. G. S. Snider and R. S. Williams. Nano/CMOS architectures using a field-programmable nanowire interconnect. Nanotechnology, 18, Jan. 2007. art. 035204.
52. H. H. Solak. Nanolithography with coherent extreme ultraviolet light. J. Phys. D, 39:R171-R178, May 2006.
53. M. R. Stan et al. Molecular electronics. Proc. IEEE, 91:1940-1957, Nov. 2003.
54. D. B. Strukov and K. K. Likharev. CMOL FPGA: A cell-based, reconfigurable architecture for hybrid digital circuits using two-terminal nanodevices. Nanotechnology, 16:888-900, Jun. 2005.
55. D. B. Strukov and K. K. Likharev. Prospects for terabit-scale nanoelectronic memories. Nanotechnology, 16:137-148, Jan. 2005.
56. D. B. Strukov and K. K. Likharev. CMOL FPGA circuits. In Proc. CDES'06, pages 213-219, 2006.
57. D. B. Strukov and K. K. Likharev. Defect-tolerant architectures for nanoelectronic crossbar memories. J. Nanoscience and Nanotechnology, 7:151-167, Jan. 2007.
58. D. B. Strukov and K. K. Likharev. Reconfigurable hybrid CMOS/nanodevice circuits for image processing. IEEE Trans. on Nanotechnology, 6:696-710, Nov. 2007.
59. D. B. Strukov and K. K. Lkharev. A reconfigurable architecture for hybrid CMOS/nanodevice circuits. In Proc. FPGA '06, pages 131-140, 2006.
60. T. F. T. Oya, T. Asai and Y. Amemiya. A majority-logic device using an irreversible single-electron box. IEEE Transactions on Nanotechnology, 2:15-22, 2003.
61. D. Tu et al. Three-dimensional CMOL: Three-dimensional integration of CMOS/nanomaterial hybrid digital circuits. Micro Nano Lett., 2:40-45, Jun. 2007.
62. Ö. Türel et al. Neuromorphic architectures for nanoelectronic circuits. Int. J. Circ. Theory App., 32:277-302, Sep.-Oct. 2004.
63. D. J. Wagner and A. H. Jayatissa. Nanoimprint lithography: Review of aspects and applications. Proc. SPIE, 6002:136-144, Nov. 2005.
64. K. L. Wang, A. Khitun, and A. H. Flood. Interconnects for nanoelectronics. IEEE 2005 International Interconnect Technology Conference, pages 231-233, 2005.
65. R. Waser and M. Aono. Nanoionics-based resistive switching memories. Nature Materials, 6:833-840, Nov. 2007.
66. X. Wu, C. Liu, L. Li, P. Jones, R. Chantrell, and D. Weller. Nonmagnetic shell in surfactant-coated FePt nanoparticles. J. Appl. Phys., 95:6810-6812, 2004.