Cortical models onto CMOL and CMOS - Architectures and performance/price

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 11 SPEC. ISS., 2007, Pages 2502-2515

  Gao, Changjian ^a   Hammerstrom, Dan ^a  

^a Portland State University   (United States)

Author keywords

Architecture performance and price; Hierarchical distributed memory (HDM); Multiplexing circuit design; Nanoelectronics

Indexed keywords

CMOS INTEGRATED CIRCUITS; MEMORY ARCHITECTURE; NANOELECTRONICS;

ANALOG CMOS CIRCUIT; CIRCUIT DESIGNS; DATA REPRESENTATIONS; DISTRIBUTED MEMORY; NANOSCALE CIRCUITS; NANOWIRE CROSSBARS; SPIKING NEURAL MODELS; TIME MULTIPLEXING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 44649101666     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.907830     Document Type: Article

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