Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal-oxide-semiconductor-molecular circuits

Nanotechnology

Volumn 17, Issue 1, 2006, Pages 89-99

  Masoumi, Massoud ^a   Raissi, Farshid ^a   Ahmadian, Mahmoud ^a   Keshavarzi, Parviz ^b  

^a K N TOOSI UNIVERSITY OF TECHNOLOGY   (Iran)

^b SEMNAN UNIVERSITY   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CRYPTOGRAPHY; MOLECULAR DYNAMICS;

ENCRYPTION ALGORITHM; GATE PLACEMENT;

CMOS INTEGRATED CIRCUITS;

EID: 29144465054     PISSN: 09574484     EISSN: 13616528     Source Type: Journal    
DOI: 10.1088/0957-4484/17/1/015     Document Type: Article

References (22)

1. Likharev K 2003 Electronics below 10 nm Nano and Giga Challenges in Microelectronics (Amsterdam: Elsevier) pp 27-68
2. Fortes J 2003 Future challenges in VLSI system design Proc. IEEE Computer Society Annual Symp. on VLSI (Tampa, FL, Feb. 2003) (Los Alamitos, CA: IEEE Computer Society Press) pp 5-7
3. Zhirnov V V and Herr D J C 2001 New frontiers: self-assembly and nanoelectronics IEEE Comput. J. 34 34-43
4. Mantooth B A and Weiss P S 2003 Fabrication, assembly, and characterization of molecular electronic components Proc. IEEE 91 1785-802
5. Ziegler M M and Stan M R 2003 CMOS/nano co-design for crossbar-based molecular electronic systems IEEE Trans. Nanotechnol. 2 217-30
6. Likharev K and Strukov D 2004 CMOL: devices, circuits, and architectures available online at http://www-mcg.uni-regensburg.de/pages/admol/book/chapter_16.html
7. Strukov D B and Likharev K K 2005 CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices Nanotechnology 16 888-900
8. Daemen J and Rijmen V 2000 Rijndael Block Cipher, AES Proposal (Computer Security Resource Center, National Institute of Standards and Technology)
9. Daemen J and Rijmen V 2002 The Design of Rijndael (Berlin: Springer)
10. Nechvatal J, Barker E, Bassham L, Burr W, Dworkin M, Foti J and Roback E 2001 Report on the Development of the Advanced Encryption Standard (AES) (NIST Administration)
11. 2000 3rd Advanced Encryption Standard Algorithm Conf. (NewYork, April 2000)
12. Zhang X and Parhi K K 2002 Implementation approaches for the advanced encryption standard algorithm IEEE Circuits Mag. 2 24-46
13. Zhang X and Parhi K K 2004 High speed VLSI architectures for the AES algorithm IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12 957-67
14. Sklavos N and Koufopavlou O 2002 Architectures and VLSI implementation of the AES-proposal Rijndael IEEE Trans. Comput. 51 1454-9
15. Kuo H and Verbauwhede I 2001 Architectural optimization for a 1.82Gbits/sec VLSI implementation of the Rijndael algorithm Proc. CHES (Paris, May 2001) pp 51-64
16. Fisvher V and Drutarovsky M 2001 Two methods of Rijndael implementation in reconfigurable hardware Proc. CHES (Paris, May 2001) pp 77-92
17. Morioka S and Satoh A 2002 An optimized S-BOX circuit architecture for low power AES design Proc. CHES (San Francisco, Aug. 2002) pp 173-86
18. Saputra H, Vijaykrishnan V, Kandemir M, Irwin M J and Brooks R 2003 Masking the energy behavior of encryption algorithms IEE Proc. Comput. Digit. Tech. 150 274-84
19. Strukov D and Likharev K 2005 Prospects for terabit-scale nanoelectronic memories Nanotechnology 16 137-8
20. Data Encryption Standard (DES) 1993 Federal Information Processing Standards, Pub. 46-2
21. Kocher P 1999 Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems Advances in Cryptology, Proc. Crypto'96 (Springer Lectures Notes in Computer Science vol 1109) ed N Kobiltz (Berlin: Springer) pp 104-13
22. Kocher P, Jaffe J and Jun B 1999 Differential power analysis Advances in Cryptology, Proc. Crypto'99 (Springer Lectures Notes in Computer Science vol 1666) ed M Wiener (Berlin: Springer) pp 275-86