Synchronous ultra-high-density 2RW dual-port 8T-SRAM with circumvention of simultaneous common-row-access

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 3, 2009, Pages 977-986

  Nii, Koji ^a   Tsukamoto, Yasumasa ^a   Yabuuchi, Makoto ^a   Masuda, Yasuhiro ^b   Imaoka, Susumu ^b   Usui, Keiichi ^c   Ohbayashi, Shigeki ^a   Makino, Hiroshi ^d   Shinohara, Hirofumi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Renesas Electronics Corporation   (Japan)

^c Daioh Electric Corp   (Japan)

^d OSAKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

65 nm; CMOS; Dual port; Embedded SRAM; High density; Low power; Low voltage; Memory; Stability; Two port; Variability

Indexed keywords

CMOS INTEGRATED CIRCUITS; DYNAMIC POSITIONING; PERCOLATION (SOLID STATE);

65 NM; CMOS; DUAL-PORT; EMBEDDED SRAM; HIGH DENSITY; LOW POWER; LOW VOLTAGE; MEMORY; TWO-PORT; VARIABILITY;

STATIC RANDOM ACCESS STORAGE;

EID: 61449171280     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2013766     Document Type: Article

References (24)

1. M. Yamashina, T. Enomoto, T. Kunio, 1. Tamitani, H. Harasaki, T. Nishitani, M. Satoh, and K. Kikuchi, "A micro programmable real-time video signal processor (VSP) LSI," IEEE J. Solid-State Circuits, vol. SSC-22, pp. 1117-1123, Dec. 1987.
2. M. Inamori, J. Naganuma, and M. Endo, "A memory-based architecture for MPEG2 system protocol LSIs," IEEE Trans. VLSI Syst., vol. 7, no. 3, pp. 339-344, Sep. 1999.
3. C.-W. Yoon, R. Woo, J. Kook, S.-J. Lee, K. Lee, and H.-J. Yeo, "An 80/20-MHz 160-mW multimedia processor integrated with embedded dram, MPEG-4 accelerator and 3-D rendering engine for mobile applications," IEEE J. Solid-Stale Circuits, vol. 36, no. 11, pp. 1758-1767, Nov. 2001.
4. H.-J. Stolberg, S. Moch, L. Friebe, A. Dehnhardt, M. B. Kulaczewski, M. Berekovic, and P. Pirsch, "An SoC with two multimedia DSPs and a RISC core for video compression applications," in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 330-531.
5. J. Kim, Y. Choi, J. Jeong, S. Lee, and S. Kim, "The v2.0 + EDR Bluetooth SoC architecture for multimedia," IEEE Trans. Consum. Electron., vol. 52, no. 2, pp. 436-444, May 2006.
6. T. Shiota, K. Kawasaki, Y. Kawabe, W. Shibamoto, A. Sato, T. Hashimoto. F. Hayakawa, S. Tago, H. Okano, Y. Nakamura, H. Miyake, A. Suga, and H. Takahashi, "A 51.2 GOPS 1.0 GB/s-DMA single-chip multi-processor integrating quadruple 8-way VLIW processors," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 194-593.
7. M. Nakajima, T. Yamamoto, M. Yamasaki, K. Kaneko, and T. Hosoki, "Homogeneous dual-processor core with shared LI cache for mobile multimedia SoC," in Symp. VLSI Circuits 2007 Dig. Tech. Papers, Jun. 2007, pp. 216-217.
8. H. Wei, R. V. Joshi, and W. H. Henkels, "A 500-MHz, 32-word × 64-bit, eight-port self-resetting CMOS register file," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 56-67, May 1999.
9. R. K. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. R. Shanbhag, K. Soumyanath, and S. Y. Borkar, "A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 624-632, May 2002.
10. N. Tzartzanis and W. W. Walker, "A differential current-mode sensing method for high-noise-immunity, single-ended register files," in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 506-543.
11. M. Miyama, J. Miyakoshi, Y. Kuroda, K. Imamura, H. Hashimoto, and M. Yoshimoto, "A sub-mW MPEG-4 motion estimation processor core for mobile video application," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1562-1570, Sep. 2004.
12. 2 8T-thin cell using dynamically-controlled column bias scheme," in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 508-543.
13. 2 8T-cell for SoC," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2006, pp. 162-163.
14. T. Suzuki, H. Yamauchi, Y. Yamagami, K. Satomi, and H. Akamatsu, "A stable 2-port SRAM cell design against simultaneously read/write-disturbed accesses," IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2109-2119, Sep. 2008.
15. S. Ishikura, M. Kurumada, T. Terano, Y. Yamagami, N. Kotani, K. Satomi, K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, T. Oashi, H. Makino, H. Shinohara, and H. Akamatsu, "A 45-nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 938-945, Apr. 2008.
16. K. Nii, Y. Tsukamoto, T. Yoshizawa, S. Imaoka, Y. Yamagami, T. Suzuki, A. Shibayama, H. Makino, and S. Iwade. "A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 684-693, Apr. 2004.
17. S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, T. Yoshihara, M. Igarashi, M. Takeuchi, H. Kawashima, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, and H. Shinohara, "A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 820-829, Apr. 2007.
18. Y. Tsukamoto, K. Nii, S. Imaoka, Y. Oda, S. Ohbayashi, T. Yoshizawa, H. Makino, K. Ishibashi, and H. Shinohara, "Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability," in ICCAD Dig., 2005, pp. 398-405.
19. K. Zhang, U. Bhattacharya, C. Zhanping, F. Hamzaoglu, D. Murray, N. Vallepalh, Y. Wang, B. Zheng, and M. Bohr, "A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 146-151, Jan. 2006.
20. M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, "90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 705-711, Mar. 2006.
21. H. Pilo, C. Barwin, G. Braceras, C. Browning. S. Lamphier, and F. Towler, "An SRAM design in 65-nm technology node featuring read and write-assist circuits to expand operating voltage," IEEE J. Solid-State Circuits, vol. 42. no. 4, pp. 813-819, Apr. 2007.
22. M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino, Y. Yamagami, S. Ishikura, T. Terano, T. Oashi, K. Hashimoto, A. Sebe. G. Okazaki, K. Satomi, H. Akamatsu, and H. Shinohara, "A 45 nm low-standby-power embedded SRAM with improved immunity against process and temperature variations," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 326-327.
23. D. P. Wang, H. J. Liao, H. Yamauchi, Y. H. Chen, Y. L. Lin, S. H. Lin, D. C. Liu, H. C. Chang, and W. Hwang, "A 45 nm dual-port SRAM with write and read capability enhancement at low voltage," in SoC Conf. Dig, Tech. Papers, Sep. 2007, pp. 211-214.
24. K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, Y. Oda, K. Usui, T. Kawamura, N. Tsuboi, T. Iwasaki, K. Hashimoto, H. Makino, and H. Shinohara, "A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, pp. 212-213.