A 65 nm ultra-high-density dual-port SRAM with 0.71um2 8T-cell for SoC

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2006, Pages 130-131

  Nii, K ^a   Masuda, Y ^b   Yabuuchi, M ^a   Tsukamoto, Y ^a   Ohbayashi, S ^a   Imaoka, S ^b   Igarashi, M ^a   Tomita, K ^a   Tsuboi, N ^a   Makino, H ^a   Ishibashi, K ^a   Shinohara, H ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Renesas Design Corporation   (Japan)

Author keywords

65nm; 8T cell SNM; Dual port; Hp90; SEAM; SoC

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECODING; SYNCHRONIZATION;

8T CELL SNM; KEEPS CELL STABILITY;

STATIC RANDOM ACCESS STORAGE;

EID: 39749102960     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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