Homogenous dual-processor core with shared L1 cache for mobile multimedia SoC

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2007, Pages 216-217

  Nakajima, Masaitsu ^a   Yamamoto, Takao ^a   Yamasaki, Masayuki ^a   Kaneko, Keisuke ^a   Hosoki, Tetsu ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; MULTIMEDIA SERVICES;

CACHE CONTROLLERS; MOBILE MULTIMEDIA;

CACHE MEMORY;

EID: 39749175119     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2007.4342724     Document Type: Conference Paper

References (3)

1. M. Nakajima et al, "Instruction Parallel Processor (IPP) Architecture on Panasonic Integrated Platform for Digital CE," Spring Processor Forum, May 2005.
2. P. Middleton, "A New ARMv6 Symmetric Multi-processing Core," Embedded Processor Forum 2004, May 2004
3. T. Kamei, "An Enhanced SuperH Core for Low-power MP Systems." Fall Microprocessor Forum 2006, December 2006.