A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 5, 2002, Pages 624-632

  Krishnamurthy, Ram K ^a,b   Alvandpour, Atila ^a,b   Balamurugan, Ganesh ^a,c   Shanbhag, Naresh R ^c   Soumyanath, K ^a,b   Borkar, Shekhar Y ^a,b  

^a IEEE   (United States)

^b INTEL CORPORATION   (United States)

^c University of Illinois at Urbana Champaign   (United States)

Author keywords

Bitline active leakage; DC noise robustness; Dual threshold voltage; Pseudostatic; Register files

Indexed keywords

BITLINE ACTIVE LEAKAGE; DC NOISE ROBUSTNESS; DUAL THRESHOLD VOLTAGE; PSEUDOSTATIC TECHNIQUE; REGISTER FILE;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENT CONTROL; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC GATES; MOSFET DEVICES; OPTIMIZATION; SIGNAL TO NOISE RATIO; THRESHOLD VOLTAGE;

MICROPROCESSOR CHIPS;

EID: 0036564731     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.997856     Document Type: Article

References (11)

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