A 45 nm 2-port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 4, 2008, Pages 938-943

  Ishikura, Satoshi ^b   Kurumada, Marefusa ^b   Terano, Toshio ^b   Yamagami, Yoshinobu ^b   Kotani, Naoki ^b   Satomi, Katsuji ^b   Nii, Koji ^a,c   Yabuuchi, Makoto ^c   Tsukamoto, Yasumasa ^c   Ohbayashi, Shigeki ^c   Oashi, Toshiyuki ^c   Makino, Hiroshi ^c   Shinohara, Hirofumi ^c   Akamatsu, Hironori ^a,b  

^a IEEE

^b Semiconductor Company   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

2 port SRAM; 8T cell; Hierarchical bit line; Misread; Simultaneous read write access; Single bit line

Indexed keywords

ACCESS CONTROL; AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; HIERARCHICAL SYSTEMS; THRESHOLD VOLTAGE; TRANSISTORS;

HIERARCHICAL BIT LINE; SIMULTANEOUS READ/WRITE ACCESS; SINGLE BIT LINE;

STATIC RANDOM ACCESS STORAGE;

EID: 41549166853     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.917568     Document Type: Conference Paper

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