A 90nm dual-port SRAM with 2.04μm 2 8T-thin cell using dynamically-controlled column bias scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Nil, Koji ^a   Tsukamoto, Yasumasa ^a   Yoshizawa, Tomoaki ^a   Imaoka, Susumu ^a   Makino, Hiroshi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DIODE FOOTED TRANSISTORS; DUAL PORT (DP) SRAM; SINGLE PORT (SP) SRAM;

CMOS INTEGRATED CIRCUITS; DECODING; ELECTRIC RESISTANCE; IMAGE PROCESSING; LEAKAGE CURRENTS; METALLIZING; POLYSILICON; SCANNING ELECTRON MICROSCOPY; TELECOMMUNICATION SYSTEMS;

STATIC RANDOM ACCESS STORAGE;

EID: 2442680722     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. 2 High Density Embedded SRAM Technologies for 100nm Generation SOC and Beyond," Symp. on VLSI Tech. Circuits Dig., pp. 11-12, Jun. 2002.
2. http://www.umc.eom/english/process/b.asp
3. Y. Tsukamoto, et. al., "Comparison of the Interconnect Capacitances of Various SRAM Cell Layouts to Achieve High Speed, Low Power SRAM Cells," Proc. of SSDM, pp. 22-23, 2003.
4. A. Agarwal et. al., "A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron," IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 319-328, Feb. 2003.
5. K. Nii et. al., "A 90 nm Low Power 32K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications," Symp. on VLSI Circuits Dig., pp. 247-250, Jun. 2003.