A memory-based architecture for MPEG2 system protocol LSI's

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 3, 1999, Pages 339-344

  Inamori, Minoru ^a,b   Naganuma, Jiro ^a,b   Endo, Makoto ^a,b  

^a IEEE   (Japan)

^b NTT CORPORATION   (Japan)

Author keywords

Embedded system; HW SW codesign; Memory based architecture; MPEG2 systems; Multiplexor demultiplexer; Protocol processing; VLSI

Indexed keywords

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DECODING; EMBEDDED SYSTEMS; GATES (TRANSISTOR); IMAGE CODING; MULTIPLEXING EQUIPMENT; NETWORK PROTOCOLS; REAL TIME SYSTEMS; STANDARDS;

HARDWARE/SOFTWARE CODESIGN; MOTION PICTURE EXPERTS GROUP (MPEG) STANDARDS;

VLSI CIRCUITS;

EID: 0032657958     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.784095     Document Type: Article

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