A 51.2GOPS 1.0GB/s-DMA single-chip multi-processor integrating quadruple 8-way VLIW processors

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Shiota, Tetsuyoshi ^a   Kawasaki, Ken Ichi ^a   Kawabe, Yukihito ^a   Shibamoto, Wataru ^a   Sato, Atsushi ^a   Hashimoto, Tetsutaro ^a   Hayakawa, Fumihiko ^a   Tago, Shin Ichirou ^a   Okano, Hiroshi ^a   Nakamura, Yasuki ^a   Miyake, Hideo ^a   Suga, Atsuhiro ^a   Takahashi, Hiromasa ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 27644489392     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S. Kyo et al., "A 51.2 GOPS Scalable Video Recognition Processor for Intelligent Cruise Control Based on a Linear Array of 128 4-way VLIW Processing Elements," ISSCC Dig. Tech. Papers, pp. 48-49, Feb., 2003.
2. Okano et al., "An 8-way VLIW Embedded Multimedia Processor Built in 7-layer Metal 0.311μm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 374-375, Feb., 2002.
3. T. Koda et al., "Parallel Processing using Data Localization for MPEG-2 Encoding on OSCAE Chip Multiprocessor," Proc. of IWIA'04, Jan., 2004.
4. http://www.sakamura-lab.org/TRON/ITRON/home-e.html
5. Y. Mabuchi et al., "Simultaneous Switching Noise Analysis on Bus Lines using Coupled Circuit and Electromagnetic Simulation," Electrical Performance of Electronic Packaging, pp. 203-206, 2001.