A 500-MHz, 32-word x 64-bit, eight-port self-resetting CMOS register file

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 1, 1999, Pages 56-67

  Hwang, Wei ^a,b,c,d,e,f   Joshi, Rajiv V ^a,b   Henkels, Walter H ^f  

^a IEEE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM T J Watson Research Center ^*  (United States)

^d New York Academy of Science   (United States)

^e AMERICAN PHYSICAL SOCIETY   (United States)

^f American Physical Society ^*

Author keywords

CMOS integrated circuits; Dynamic logic circuit; High speed integrated circuits; Integrated circuit design; Microprocessor; Registers

Indexed keywords

CHOPPERS (CIRCUITS); INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; MULTIPLEXING EQUIPMENT; SHIFT REGISTERS; TIMING CIRCUITS;

INPUT ISOLATION TECHNIQUE; MULTIBLOCK STRUCTURE; MULTIPLEXING CIRCUITS; SELF RESETTING CIRCUIT;

CMOS INTEGRATED CIRCUITS;

EID: 0032647363     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.736656     Document Type: Article

References (16)

1. M. Nomura, M. Yamashina, K. Suzuki, M. Izumikawa, H. Igura, H. Abiko, K. Okabe, A. Ono, T. Nakayama, and H. Yamada, "A 500 MHz, 0.4 μm CMOS, 32-word by 32-bit 3-port register file," in Proc. IEEE 1995 Custom Integrated Circuits Conf., 1995, pp. 151-154.
2. C. C. Chao and B. A. Wooly, "A 1.3 ns 32-word x 32-bit three-port BiCMOS register file," IEEE J. Solid-State Circuits, vol. 31, pp. 758-765, June 1996.
3. F. Murabayashi, T. Yamauchi, H. Yamada, T. Nishiyama, K. Shimamura, S. Tanaka, T. Hotta, T. Shimizu, and H. Sawamoto, "2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor," IEEE J. Solid-State Circuits, vol. 31, pp. 972-980, June 1996.
4. J. Montànaro, R. T. Witek, K. Anne, A. J. Black, E. M. Cooper, D. W. Dobberpuhl, P. M. Donahue, J. Eno, G. W. Hoeppner, D. Kruckemyer, T. H. Lee, P. Lin, L. Maddern, D. Murray, M. Pearce, S. Santhanam, K. J. Snyder, R. Stephany, and S. C. Thierauf, "A 160-MHz, 32-b, 0.5 W CMOS RISC microprocessor," IEEE J. Solid-State Circuits, vol. 31, pp. 1703-1714, Nov. 1996.
5. C. F. Webb, C. J. Anderson, L. Sigal, K. L. Shepard, J. D. Warnock, B. Curran, B. W. Krumm, M. D. Mayo, P. J. Camporese, E. M. Schwarz, M. S. Farrell, P. J. Restle, R. M. Averill III, T. J. Siegel, W. V. Huott, Y. H. Chan, B. Wile, P. G. Emma, D. K. Beece, C. T. Chuang, and C. Price, "A 400 MHz S/390 microprocessor," in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 168-169.
6. B. A. Gieseke, R. L. Allmon, D. W, Bailey, B. J. Benschneider, S. M. Britton, J. D. Clouser, H. R. Fair, J. A. Farrel, M. K. Gowan, C. L. Houghton, J. B. Keller, T. H. Lee, D. L. Leibholz, S. C. Lowell, M. D. Matson, R. J. Matthew, V. Peng, M. D. Quinn, D. A. Priore, M. J. Smith, and K. E. Wilcox, "A 600 MHz superscalar RISC microprocessor with out-of-order execution," in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 176-177.
7. T. Yoshida, Y. Shimazu, A. Yamada, E. Holmann, K. Nakakimura, H. Takata, M. Kitao, T. Kishi, H. Kobayaashi, M. Sato, A. Mohri, K. Suzuki, Y. Ajioka, and K. Higashitani, "A 2 V 250 MHz multimedia processor," in ISSCC Dig. Tech. Papers, Feb. 1997, pp. 266-267.
8. H. Hara, T. Sakurai, T. Nagamatsu, K. Seta, H. Momose, Y. Niitsu, H. Miyakawa, K. Matsuda, Y. Watanabe, F. Sano, and A. Chiba, "0.5 μm 3.3 V BiCMOS standard cells with 32-kilobyte cache and ten-port register file," IEEE J. Solid-State Circuits, vol. 27, pp. 1579-1583, Nov. 1992.
9. C. Asato, "A 14-Port 3.8 ns 116 word 64-b read renaming register file," IEEE J. Solid-Stale Circuits, vol. 30, pp. 1254-1258, Nov. 1995.
10. M. Izumikawa and M. Yamashina, "A current direction sense technique for multiport SRAM's," IEEE J. Solid-State Circuits, vol. 31, pp. 546-551, Apr. 1996.
11. C. W. Koburger, W, F. Clark, J. W. Adkisson, E. Adler, P. E. Bakeman, A. S. Bergendahl, A. B. Botula, W. Chang, B. Davari, J. H. Givens, H. H. Hansen, S, J, Holmes, D. V. Horak, C. H. Lam, J. B. Lasky, S. E. Luce, R. W. Mann, G. L. Miles, J. S. Nakos, E. J. Nowak, G. Shahidi, Y. Taur, F. R. White, and M. R. Wordeman, "A half-micron CMOS logic generation," IBM J. Res. Develop., vol. 39, no. 1/2, pp. 215-227, Jan./Mar. 1995.
12. T. I. Chappell, B. A. Chappell, S. E. Schuster, J. W. Allen, S. P. Klepner, R. V. Joshi, and R. L. Franch, "A 2-ns cycle, 3.8 ns access 512-Kb CMOS ECL SRAM with a fully pipelined architecture," IEEE J. Solid-State Circuits, vol. 26, pp. 1577-1585, Nov. 1991.
13. W. Henkels, W. Hwang, and T. I. Chappell, "Cells and read-circuits for high performance register files," U.S. Patent 5 481 495, Jan. 2, 1996.
14. W. Henkels, W. Hwang, and R. V. Joshi, "Reset and pulse-width-control circuits for high performance multiport register files," U.S. Patent 5 617 047, Apr. 1, 1997.
15. _, "A 500 MHz 32-word x 64-bit 8-port self-resetting CMOS register file and associated dynamic-to-static latch," in 1997 Symp. VLSI Circuits Dig. Tech. Papers, June 1997, pp. 41-42.
16. W. Hwang, W. Henkels, and R. V. Joshi, "A pulse-to-static conversion latch with a self-timed control circuit," in 1997 IEEE Int. Conf. Computer Design: VLSI in Computers and Processors, Oct. 1997, pp. 712-717.