메뉴 건너뛰기




Volumn 55, Issue 11, 2008, Pages 3697-3710

Sliced message passing: High throughput overlapped decoding of high-rate low-density parity-check codes

Author keywords

High throughput; High rate low density parity check (LDPC) code; IEEE 10 GBase T standard; Overlapped decoding; Structured codes

Indexed keywords

FORWARD ERROR CORRECTION; IEEE STANDARDS; MESSAGE PASSING; SIGNAL ENCODING;

EID: 58049199413     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.926995     Document Type: Article
Times cited : (61)

References (38)
  • 1
    • 84925405668 scopus 로고
    • Low-density parity-check codes
    • Jan
    • R. Gallager, "Low-density parity-check codes," IRE Trans. Inf. Theory, vol. IT-8, no. 1, pp. 21-28, Jan. 1962.
    • (1962) IRE Trans. Inf. Theory , vol.IT-8 , Issue.1 , pp. 21-28
    • Gallager, R.1
  • 2
    • 84947903359 scopus 로고
    • Good codes based on very sparse matrices
    • D. J. C. MacKay and R. M. Neal, C. Boyd, Ed, Proc. Cryptogr. Coding 5th IMA Conf, Oct
    • D. J. C. MacKay and R. M. Neal, C. Boyd, Ed., "Good codes based on very sparse matrices," in Proc. Cryptogr. Coding 5th IMA Conf., Oct. 1995, vol. 1025, Lecture Notes in Computer Science, pp. 100-111.
    • (1995) Lecture Notes in Computer Science , vol.1025 , pp. 100-111
  • 3
    • 0030287317 scopus 로고    scopus 로고
    • A linear time erasure-resilient code with nearly optimal recovery
    • Nov
    • N. Alon and M. Luby, " A linear time erasure-resilient code with nearly optimal recovery," IEEE Trans. Inf. Theory, vol. 42, no. 6, pp. 1732-1736, Nov. 1996.
    • (1996) IEEE Trans. Inf. Theory , vol.42 , Issue.6 , pp. 1732-1736
    • Alon, N.1    Luby, M.2
  • 4
    • 0035248618 scopus 로고    scopus 로고
    • On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit
    • Feb
    • S.-Y. Chung, G. D. Forney, Jr., T. J. Richardson, and R. Urbanke, "On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit," IEEE Commun. Lett., vol. 5, no. 2, pp. 58-60, Feb. 2001.
    • (2001) IEEE Commun. Lett , vol.5 , Issue.2 , pp. 58-60
    • Chung, S.-Y.1    Forney Jr., G.D.2    Richardson, T.J.3    Urbanke, R.4
  • 5
    • 0042092025 scopus 로고    scopus 로고
    • A class of low-density parity-check codes constructed based on Reed-Solomon codes with two information symbols
    • Jul
    • I. Djunrdjevic, J. Xu, K. Abdel-Ghaffar, and S. Lin, "A class of low-density parity-check codes constructed based on Reed-Solomon codes with two information symbols," IEEE Commun. Lett., vol. 7, no. 7, pp. 317-319, Jul. 2003.
    • (2003) IEEE Commun. Lett , vol.7 , Issue.7 , pp. 317-319
    • Djunrdjevic, I.1    Xu, J.2    Abdel-Ghaffar, K.3    Lin, S.4
  • 6
    • 31744435016 scopus 로고    scopus 로고
    • Algebraic construction of sparse matrices with large girth
    • Feb
    • M. E. O'Sullivan, "Algebraic construction of sparse matrices with large girth," IEEE Trans. Inf. Theory, vol. 52, no.2, pp. 718-727, Feb. 2006.
    • (2006) IEEE Trans. Inf. Theory , vol.52 , Issue.2 , pp. 718-727
    • O'Sullivan, M.E.1
  • 7
    • 58049208867 scopus 로고    scopus 로고
    • Digital Video Broadcasting (DVB); Second Generation, ETSI EN 302 307 2005, 1.1.
    • "Digital Video Broadcasting (DVB); Second Generation," ETSI EN 302 307 2005, vol. 1.1.
  • 8
    • 84856737677 scopus 로고    scopus 로고
    • Online, Available
    • IEEE 10 GBase-T Task Force [Online]. Available: http://grouper.ieee.org/ groups/802/3/an/index.html
    • IEEE 10 GBase-T Task Force
  • 9
    • 58049207356 scopus 로고    scopus 로고
    • IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems Amendment for Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands, IEEE 802.16e-2005, 2005 [Online]. Available: http://standards.ieee.org/getieee802/download/ 802.16e-2005.pdf
    • IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems Amendment for Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands, IEEE 802.16e-2005, 2005 [Online]. Available: http://standards.ieee.org/getieee802/download/ 802.16e-2005.pdf
  • 10
    • 85008048513 scopus 로고    scopus 로고
    • Decoding behavior study of LDPC codes under a realistic magnetic recording channel model
    • Oct
    • X. Hu, B. V. K. V. Kumar, L. Sun, and J. Xie, "Decoding behavior study of LDPC codes under a realistic magnetic recording channel model," IEEE Trans. Magn., vol. 42, no. 10, pp. 2606-2608, Oct. 2006.
    • (2006) IEEE Trans. Magn , vol.42 , Issue.10 , pp. 2606-2608
    • Hu, X.1    Kumar, B.V.K.V.2    Sun, L.3    Xie, J.4
  • 11
    • 0344981526 scopus 로고    scopus 로고
    • Low-density parity-check decoder architecture for high throughput optical fiber channels
    • Oct
    • A. Selvarathinam, E. Kim, and G. Choi, "Low-density parity-check decoder architecture for high throughput optical fiber channels," in Proc. IEEE Int. Conf. Comput. Des., Oct. 2003, pp. 520-525.
    • (2003) Proc. IEEE Int. Conf. Comput. Des , pp. 520-525
    • Selvarathinam, A.1    Kim, E.2    Choi, G.3
  • 13
    • 33644640388 scopus 로고    scopus 로고
    • A 640-Mb/s 2048-bit programmable LDPC decoder chip
    • Mar
    • M. M. Mansour and N. R. Shanbhag, " A 640-Mb/s 2048-bit programmable LDPC decoder chip," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 684-698, Mar. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.3 , pp. 684-698
    • Mansour, M.M.1    Shanbhag, N.R.2
  • 14
  • 15
    • 67649112194 scopus 로고    scopus 로고
    • Multi-gbit/sec low density parity check decoders with reduced interconnect complexity
    • May
    • A. Darabiha, A. C. Carusone, and F. R. Kschischang, " Multi-gbit/sec low density parity check decoders with reduced interconnect complexity," in Proc. IEEE Int. Symp. Circuits Syst., May 2005, vol. 5, pp. 5194-5197.
    • (2005) Proc. IEEE Int. Symp. Circuits Syst , vol.5 , pp. 5194-5197
    • Darabiha, A.1    Carusone, A.C.2    Kschischang, F.R.3
  • 16
    • 0036504121 scopus 로고    scopus 로고
    • A 690-mW 1-gb/s 1024-b, rate-1/2 low-density parity-check code decoder
    • Mar
    • A. J. Blanksby and C. J. Howland, "A 690-mW 1-gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE J. Solid-State Circuits vol. 37, no. 3, pp. 404-412, Mar. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.3 , pp. 404-412
    • Blanksby, A.J.1    Howland, C.J.2
  • 17
    • 58049212466 scopus 로고    scopus 로고
    • L. Zhou, M. Su, and C.-J. R. Shi, Maximizing low-density parity-checking code decoding throughput with c-slow retiming and asynchronous deep pipelining Dept. Elect. Eng., Univ. Washington, Washington, DC, Tech. Rep. UW-EE-2006, Dec. 2006.
    • L. Zhou, M. Su, and C.-J. R. Shi, Maximizing low-density parity-checking code decoding throughput with c-slow retiming and asynchronous deep pipelining Dept. Elect. Eng., Univ. Washington, Washington, DC, Tech. Rep. UW-EE-2006, Dec. 2006.
  • 18
    • 58049196275 scopus 로고    scopus 로고
    • L. Zhou, C. Wakayama, N. Jangkrajarng, B. Hu, and C.-J. R. Shi, Implementing a 2-Gb/s 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits Dept. Elect. Eng., Univ. Washington, Washington, DC, Tech. Rep. UW-EE-2006, Dec. 2006 [Online]. Available: http://www.ee.washington.edu/research
    • L. Zhou, C. Wakayama, N. Jangkrajarng, B. Hu, and C.-J. R. Shi, Implementing a 2-Gb/s 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits Dept. Elect. Eng., Univ. Washington, Washington, DC, Tech. Rep. UW-EE-2006, Dec. 2006 [Online]. Available: http://www.ee.washington.edu/research
  • 19
    • 10644247292 scopus 로고    scopus 로고
    • A class of group-structured LDPC codes
    • Ambleside, U.K, Jul
    • R. M. Tanner, "A class of group-structured LDPC codes," in Proc. ICSTA, Ambleside, U.K., Jul. 2001, pp. 365-370.
    • (2001) Proc. ICSTA , pp. 365-370
    • Tanner, R.M.1
  • 20
    • 33645807178 scopus 로고    scopus 로고
    • Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder
    • Apr
    • L. Yang, H. Liu, and C.-J. R. Shi, "Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 6. no. 892-904. Apr. 2006.
    • (2006) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.51 , Issue.6-892 -904
    • Yang, L.1    Liu, H.2    Shi, C.-J.R.3
  • 21
    • 0036954180 scopus 로고    scopus 로고
    • Low-power VLSI decoder architectures for LDPC codes
    • Monterey, CA, Aug
    • M. M. Mansour and N. R. Shanbhag, "Low-power VLSI decoder architectures for LDPC codes," in Proc. ISLPED, Monterey, CA, Aug. 2002, pp. 284-289.
    • (2002) Proc. ISLPED , pp. 284-289
    • Mansour, M.M.1    Shanbhag, N.R.2
  • 22
    • 3042549356 scopus 로고    scopus 로고
    • Overlapped message passing for quasi-cyclic low-density parity check codes
    • Jun
    • Y. Chen and K. K. Parhi, "Overlapped message passing for quasi-cyclic low-density parity check codes," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 6, pp. 1106-1113, Jun. 2004.
    • (2004) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.51 , Issue.6 , pp. 1106-1113
    • Chen, Y.1    Parhi, K.K.2
  • 23
    • 39049131175 scopus 로고    scopus 로고
    • VLSI design of high-rate quasi-cyclic LDPC codes for magnetic recording channel
    • Sep
    • H. Zhong, T. Zhang, and E. Haratsch, "VLSI design of high-rate quasi-cyclic LDPC codes for magnetic recording channel," in Proc. IEEE CICC, Sep. 2006, pp. 325-328.
    • (2006) Proc. IEEE CICC , pp. 325-328
    • Zhong, H.1    Zhang, T.2    Haratsch, E.3
  • 25
    • 0035150335 scopus 로고    scopus 로고
    • VLSI implementation-oriented (3, k -regular low-density parity-check codes
    • Sep
    • T. Zhang and K. K. Parhi, "VLSI implementation-oriented (3, k -regular low-density parity-check codes," in Proc. IEEE Workshop Signal Process. Syst., Sep. 2001, pp. 25-36.
    • (2001) Proc. IEEE Workshop Signal Process. Syst , pp. 25-36
    • Zhang, T.1    Parhi, K.K.2
  • 27
    • 33744545447 scopus 로고    scopus 로고
    • Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes
    • Kobe, Japan, May
    • Z. Wang and Q. Jia, "Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes," in Proc. IEEE ISCAS, Kobe, Japan, May 2005, vol. 6, pp. 5786-5789.
    • (2005) Proc. IEEE ISCAS , vol.6 , pp. 5786-5789
    • Wang, Z.1    Jia, Q.2
  • 28
    • 4544242348 scopus 로고    scopus 로고
    • Area efficient decoding of quasi-cyclic low density parity check codes
    • Montreal, QC, Canada, May
    • Z. Wang, Y. Chen, and K. K. Parhi, "Area efficient decoding of quasi-cyclic low density parity check codes," in Proc. ICASSP, Montreal, QC, Canada, May 2004, vol. 5, pp. V-49-V-52.
    • (2004) Proc. ICASSP , vol.5
    • Wang, Z.1    Chen, Y.2    Parhi, K.K.3
  • 29
    • 0036493854 scopus 로고    scopus 로고
    • Near optimum universal belief propagation based decoding of low-density parity check codes
    • Mar
    • J. Chen and M. P. C. Fossorier, "Near optimum universal belief propagation based decoding of low-density parity check codes," IEEE Trans. Commun., vol. 50, no. 3, pp. 406-414, Mar. 2002.
    • (2002) IEEE Trans. Commun , vol.50 , Issue.3 , pp. 406-414
    • Chen, J.1    Fossorier, M.P.C.2
  • 30
    • 17944400187 scopus 로고    scopus 로고
    • Efficient implementations of the sum-product algorithm for decoding LDPC codes
    • San Antonio, TX, Nov
    • X.-Y. Hu, E. Eleftheriou, D.-M. Arnold, and A. Dholakia, "Efficient implementations of the sum-product algorithm for decoding LDPC codes," in Proc. GLOBECOM Conf., San Antonio, TX, Nov. 2001, vol. 2, pp. 1036-1036E.
    • (2001) Proc. GLOBECOM Conf , vol.2
    • Hu, X.-Y.1    Eleftheriou, E.2    Arnold, D.-M.3    Dholakia, A.4
  • 32
    • 34547502024 scopus 로고    scopus 로고
    • T. Mohsenin and B. M. Baas, High-throughput LDPC decoders using a multiple split-row method, in Proc. ICASSP, Honolulu, HI, Apr. 2007, 2, pp. II-13-II-16.
    • T. Mohsenin and B. M. Baas, "High-throughput LDPC decoders using a multiple split-row method," in Proc. ICASSP, Honolulu, HI, Apr. 2007, vol. 2, pp. II-13-II-16.
  • 33
    • 33749160113 scopus 로고    scopus 로고
    • A 3.33 Gb/s (1200, 720) low-density parity check code decoder
    • Sep
    • C. Lin et al., "A 3.33 Gb/s (1200, 720) low-density parity check code decoder," in Proc. IEEE ESSCIRC, Sep. 2005, pp. 211-214.
    • (2005) Proc. IEEE ESSCIRC , pp. 211-214
    • Lin, C.1
  • 34
    • 33646533730 scopus 로고    scopus 로고
    • Loosely coupled memory-based decoding architecture for low density parity check codes
    • May
    • S. Kang and I. Park, "Loosely coupled memory-based decoding architecture for low density parity check codes," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 5, pp. 1045-1056, May 2006.
    • (2006) IEEE Trans. Circuits Syst. I, Reg. Papers , vol.53 , Issue.5 , pp. 1045-1056
    • Kang, S.1    Park, I.2
  • 35
    • 33750591782 scopus 로고    scopus 로고
    • Degree-matched check node decoding for regular and irregular LDPCs
    • Oct
    • S. L. Howard;, C. Schlegel, and V. C. Gaudet, "Degree-matched check node decoding for regular and irregular LDPCs," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 10, pp. 1054-1058, Oct. 2006.
    • (2006) IEEE Trans. Circuits Syst. II, Exp. Briefs , vol.53 , Issue.10 , pp. 1054-1058
    • Howard, S.L.1    Schlegel, C.2    Gaudet, V.C.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.