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Volumn 42, Issue 10, 2006, Pages 2606-2608

Decoding Behavior Study of LDPC Codes Under a Realistic Magnetic Recording Channel Model

Author keywords

EPR4; FPGA; LDPC code; magnetic recording; nonlinear transition shift; partial erasure

Indexed keywords


EID: 85008048513     PISSN: 00189464     EISSN: 19410069     Source Type: Journal    
DOI: 10.1109/TMAG.2006.878652     Document Type: Article
Times cited : (7)

References (10)
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    • L. Sun, H. Song, B. V. K. V. Kumar, and Z. Keirn, “Field-programmable gate-array-based investigation of the error floor of low-density parity check codes for magnetic recording channels,” IEEE Trans. Magn., vol. 41, no. 10, pp. 2983–2985, Oct. 2005.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.