Loosely coupled memory-based edcoding architecture for low density parity check codes

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 5, 2006, Pages 1045-1056

  Kang, Se Hyeon ^a   Park, In Cheol ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Channel coding; Decoder; Factor graph; Low density parity check (LDPC) code; Matrix permutation; Scheduling

Indexed keywords

CODES (SYMBOLS); DATA FLOW ANALYSIS; MATRIX ALGEBRA; PARALLEL PROCESSING SYSTEMS; SCHEDULING;

CHANNEL CODING; FACTOR GRAPH; LOW DENSITY PARITY CHECK CODES; MATRIX PERMUTATION;

DECODING;

EID: 33646533730     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.862181     Document Type: Article

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