A versatile variable rate LDPC codec architecture

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 54, Issue 10, 2007, Pages 2240-2251

  Fewer, Colm P ^a   Flanagan, Mark F ^a   Fagan, Anthony D ^a  

^a UNIVERSITY COLLEGE DUBLIN   (Ireland)

Author keywords

Implementation; Low density parity check (LDPC) codes; Puncturing; Rate compatible; Versatile

Indexed keywords

COMPUTER HARDWARE; DATA PROCESSING; SWITCHING;

DECODER; DYNAMIC SWITCHING; ENCODER; LOW-DENSITY PARITY-CHECK CODES; PUNCTURE-BASED SYSTEM; RATE COMPATIBILITY;

CODES (SYMBOLS);

EID: 36348981212     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2007.904641     Document Type: Article

References (29)

1. R. Gallager, "Low-density parity-check codes," IEEE Trans. Inf. Theory, vol. IT-8, no. 1, pp. 21-28, Jan. 1962.
2. D. MacKay and R. Neal, "Good codes based on very sparse matrices," presented at the IMA Conf. Cryptography and Coding, 1995.
3. D. MacKay, "Good error correcting codes based on very sparse matrices," IEEE Trans. Inf. Theory, vol. 45, no. 2, pp. 399-431, Mar. 1999.
4. N. Alon and M. Luby, "A linear time erasure-resiliant code with nearly optimal recovery," IEEE Trans. Inf. Theory, vol. 42, no. 6, pp. 1732-1736, Nov. 1996.
5. T. J. Richarson, M. A. Shokrollahi, and R. L. Urbanke, "Design of capacity-approaching irregular low-density parity-check codes," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 619-637, Feb. 2001.
6. T. J. Richarson and R. L. Urbanke, "The capacity of low-density parity-check codes under message-passing decoding," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 599-618, Feb. 2001.
7. S. Chung, G. Forney, T. Richardson, and R. Urbanke, "On the design of low-density parity-check codes within 0.0045 db of the Shannon limit," IEEE Commun. Lett., vol. 5, no. 2, pp. 58-60, Feb. 2001.
8. A. Blanksby and C. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE J. Solid-State Circuits vol. 37, no. 3, pp. 404-412, Mar. 2002.
9. J. K. Lee, B. Lee, J. Thorpe, K. Andrews, S. Dolinar, and J. Hamkins, "A scalable architecture of a structured LDPC decoder," in Proc. Int. Symp. Inf. Theory, 2004, p. 292.
10. D. E. Hocevar, "LDPC code construction with flexible hardware implementation," in Proc. Int. Conf. Communications, May 2003, pp. 2801-2712.
11. M. Mansour and N. Shanbhag, "High throughput LDPC decoders," IEEE Trans. Very Large Scale Integr. Syst., vol. 11, no. 6, pp. 976-996, Dec. 2003.
12. H. Zhong and T. Zhang, "Block LDPC: A practical LDPC coding system design approach," IEEE Trans. Circuits Syst., vol. 52, no. 4, pp. 766-775, Apr. 2005.
13. T. J. Richarson and R. L. Urbanke, "Efficient encoding of low-density parity-check codes," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 638-656, Feb. 2001.
14. D. Lee, W. Luk, C. Wang, C. Jones, M. Smith, and J. Villasenor, "Low-density parity-check code constructions for hardware implementation," in Proc. IEEE Symp. Field-Programmable Custom Computing Machines, 2004, pp. 101-111.
15. L. Sun and B. V. K. V. Kumar, "Field programmable gate array implementation of a generalized decoder for structured low-density parity check codes," in Proc. IEEE Int. Conf. Field-Programmable Technology, 2004, pp. 17-24.
16. D. Sridhara, T. Fuja, and R. M. Tanner, "Low density parity check codes from permutation matrices," presented at the John Hopkins Conf. Information Sciences and Systems, 2001.
17. S. Myung, K. Yang, and J. Kim, "Quasi-cyclic LDPC codes for fast encoding," IEEE Trans. Inf. Theory, vol. 51, no. 8, pp. 2894-2901, Aug. 2005.
18. R. L. Urbanke, LDPCOpt - A Tool for Determination of Optimal Degree Distributions. [Online]. Available: http://lthcwww.epfl.ch/research/ index.php
19. T. Tian, C. Jones, J. D. Villasenor, and R. D. Wesel, "Construction of irregular LDPC codes with low error floors," in Proc. IEEE Int. Conf. Communications, May 2003, pp. 3125-3129.
20. J. Kang and P. Fan, "Flexible construction of irregular partitioned permutation LDPC codes with low error floors," IEEE Commun. Lett. vol. 9, no. 6, pp. 534-536, Jun. 2005.
21. M. Mansour and N. Shanbhag, "A novel design methodology for high-performance programmable decoder cores for AA-LDPC codes," in Proc. IEEE Workshop on Signal Process. Syst., Aug. 2003, pp. 29-34.
22. Z. Li, L. Chen, L. Zeng, S. Lin, and W. Fong, "Efficient encoding of quasi-cyclic low-density parity-check codes," in Proc. IEEE Globecom 2005, pp. 1205-1210.
23. Y. Kou, S. Lin, and M. P. Fossorier, "Low-density parity-check codes based on finite geometries: A rediscovery and new results," IEEE Trans. Inf. Theory, vol. 47, no. 11, pp. 2711-2736, Nov. 2001.
24. L. Miles, J. Gambles, G. Maki, W. Ryan, and S. Whitaker, "An (8158,7136) low-density parity-check encoder," in Proc. IEEE Conf. Custom Integr. Circuits, 2005, pp. 699-702.
25. F. Keinle, T. Brack, and N. Welin, "A synthesizable IP core for DVB-S2 LDPC code decoding," in Proc. Eur. Conf. Design, Autom. Test, 2005, pp. 100-105.
26. F. Keinle and N. Welin, "Design methodology for IRA codes," in Proc. ASP Des. Autom. Conf., 2004, pp. 459-462.
27. M. Rovini, N. E. L'Insalata, F. Rossi, and L. Fanucci, "VLSI design of a high-throughput multi-rate decoder for structured LDPC codes," in Proc. 8th Euromicro Conf. Digital Syst. Des., 2005, pp. 202-209.
28. H. Zhong and T. Zhang, "Joint code-encoder-decoder design for LDPC coding system VLSI implementation," in Proc. IEEE Int. Symp. Circuits and Systems, May 2004, vol. 2, pp. 389-392.
29. J. Ha, J. Kim, and S. McLaughlin, "Rate-compatible puncturing of low-density parity-check codes," IEEE Trans. Inf. Theory, vol. 50, no. 11, pp. 2824-2836, Nov. 2004.