On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit

IEEE Communications Letters

Volumn 5, Issue 2, 2001, Pages 58-60

  Chung, Sae Young ^a,b   David Forney Jr , G ^a,c   Richardson, Thomas J ^d   Urbanke, Rüdiger ^e  

^a IEEE   (United States)

^b Airvana Inc   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d QUALCOMM INC   (United States)

^e EPFL   (Switzerland)

Author keywords

Density evolution; Low density parity check codes; Shannon limit; Sum product algorithm

Indexed keywords

ADDITIVE WHITE GAUSSIAN NOISE CHANNEL; DENSITY EVOLUTION; LOW-DENSITY PARITY-CHECK CODES; SHANNON LIMIT; SUM-PRODUCT ALGORITHM;

ALGORITHMS; BIT ERROR RATE; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; DECODING; FOURIER TRANSFORMS; OPTIMIZATION; WHITE NOISE;

TURBO CODES;

EID: 0035248618     PISSN: 10897798     EISSN: None     Source Type: Journal    
DOI: 10.1109/4234.905935     Document Type: Article

References (12)

1. Design of capacity-approaching low-density parity-check codes
2. Expander codes
3. Near Shannon limit performance of low-density parity-check codes
4. Near Shannon limit error-correcting coding and decoding: Turbo-codes
5. The capacity of low-density parity-check codes under message-passing decoding
6. Finding good LDPC codes
7. Good error-correcting codes based on very sparse matrices
8. On the construction of some capacity-approaching coding schemes
9. Codes on graphs: Normal realizations
10. Iterative decoding of binary block and convolutional codes
11. Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation