Block-interlaced LDPC decoders with reduced interconnect complexity

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 55, Issue 1, 2008, Pages 74-78

  Darabiha, Ahmad ^a   Carusone, Anthony Chan ^a   Kschischang, Frank R ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

10 GB Ethernet; Channel coding; Decoder architectures; Iterative message passing; Low density parity check (LDPC) codes; Very large scale integration (VLSI)

Indexed keywords

DECODING; FORWARD ERROR CORRECTION; ITERATIVE METHODS; MESSAGE PASSING; VLSI CIRCUITS;

10-GB ETHERNET; DECODER ARCHITECTURE; HARDWARE OVERHEADS; ITERATIVE MESSAGE PASSING; LOW DENSITY PARITY CHECK DECODERS (LDPC); LOW-DENSITY PARITY-CHECK (LDPC) CODES; PARALLEL LDPC DECODERS; ROUTING CONGESTION;

CHANNEL CODING;

EID: 48749115194     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.905328     Document Type: Article

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