VLSI implementation-oriented (3,k)-regular low-density parity-check codes

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2001, Pages 25-36

  Zhang, T ^a   Parhi, K K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; DECODING; ENCODING (SYMBOLS); ERROR CORRECTION; MATRIX ALGEBRA; PARALLEL PROCESSING SYSTEMS; VLSI CIRCUITS;

GALLAGER LOW DENSITY PARITY CHECK CODES; PARITY CHECK MATRIX;

CODES (SYMBOLS);

EID: 0035150335     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Parallel decoding architectures for low density parity check codes
2. Decoder-first code design
3. Good error-correcting codes based on very sparse matrices
4. Design of good LDPC codes using girth distribution
5. On finite precision implementation of low-density parity-check codes decoder
6. Comparison of constructions of irregular gallager codes
7. Efficient encoding of low-density parity-check codes