Low-density parity-check decoder architecture for high throughput optical fiber channels

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 520-525

  Selvarathinam, Anand ^a   Kim, Euncheol ^a   Choi, Gwan ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Fibre channel; Hardware scaling; LDPC decoder; Parallel architecture; Serial architecture; VLSI

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTER HARDWARE; ERROR CORRECTION; NETWORK PROTOCOLS; OPTICAL COMMUNICATION; OPTICAL FIBERS; VLSI CIRCUITS;

FORWARD ERROR CORRECTION; HARDWARE SCALING; LOW-DENSITY PARITY-CHECK DECODER ARCHITECTURE; OPTICAL FIBER CHANNELS;

COMPUTER ARCHITECTURE;

EID: 0344981526     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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