A 640-Mb/s 2048-bit programmable LDPC decoder chip

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 3, 2006, Pages 684-697

  Mansour, Mohammad M ^a,b   Shanbhag, Naresh R ^a,c,d,e  

^a IEEE   (Lebanon)

^b AMERICAN UNIVERSITY OF BEIRUT   (Lebanon)

^c University of Illinois at Urbana Champaign   (United States)

^d UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^e VLSI Information Processing Systems (ViPS) Group   (United States)

Author keywords

Architecture aware low density parity check (AA LDPC) codes; Iterative decoders; LDPC codes; Turbodecoding message passing (TDMP) algorithm; VLSI decoder architectures

Indexed keywords

ARCHITECTURE-AWARE LOW-DENSITY PARITY-CHECK (AA-LDPC) CODES; ITERATIVE DECODERS; LDPC CODES; TURBODECODING MESSAGE-PASSING (TDMP) ALGORITHM; VLSI DECODER ARCHITECTURES;

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTATION THEORY; CONVERGENCE OF NUMERICAL METHODS; DECODING; ITERATIVE METHODS; TABLE LOOKUP;

MICROPROCESSOR CHIPS;

EID: 33644640388     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.864133     Document Type: Article

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