Low-power VLSI decoder architectures for LDPC codes

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 284-289

  Mansour, Mohammad M ^a   Shanbhag, Naresh R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

BCJR algorithm; LDPC codes; Lower power architectures

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DECODING; ELECTRIC POWER SUPPLIES TO APPARATUS; INTERCONNECTION NETWORKS; PARALLEL PROCESSING SYSTEMS; SWITCHING THEORY;

LOW DENSITY PARITY CHECK CODES; LOW POWER ARCHITECTURES; MESSAGE PASSING ALGORITHM; PARALLEL DECODER ARCHITECTURE;

VLSI CIRCUITS;

EID: 0036954180     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146756     Document Type: Conference Paper

References (7)

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