A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 3, 2002, Pages 404-412

  Blanksby, Andrew J ^a   Howland, Chris J ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

CMOS digital integrated circuits; Decoding; Error correction coding; Parallel architectures

Indexed keywords

ALGORITHMS; DECODING; ENERGY DISSIPATION; ERROR CORRECTION; PARALLEL PROCESSING SYSTEMS; PERMITTIVITY; TURBO CODES;

LOW DENSITY PARITY-CHECK (LDPC) CODE DECODERS;

CODE CONVERTERS;

EID: 0036504121     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.987093     Document Type: Article

References (17)

1. Near Shannon limit error-correcting codes and decoding
2. Near optimum decoding of product codes
3. Design and implementation of a low complexity VLSI turbo-code decoder architecture for low energy mobile wireless communications
4. Low density parity check codes
5. Design of capacity-approaching irregular low-density parity-check codes
6. On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit
7. A recursive approach to low complexity codes
8. Analysis of low density codes and improved designs using irregular graphs
9. Parallel decoding architectures for low density parity check codes
10. A Viterbi algorithm with soft-decision outputs and its applications
11. Optimal decoding of linear codes for minimizing symbol error rate
12. VLSI architectures for iterative decoders in magnetic recording channels
13. A 1-Gb/s, four-state, sliding block Viterbi decoder
14. An IC for turbo-codes encoding and decoding