Code construction and FPGA implementation of a low-error-floor multi-rate low-density parity-check code decoder

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 4, 2006, Pages 892-904

  Yang, Lei ^a   Liu, Hui ^a   Shi, C J Richard ^a  

^a University of Washington   (United States)

Author keywords

Block error rate; Channel encoding; Cycle elimination; Field programmable gate array (FPGA); Forward error correction (FEC); Low density parity check (LDPC) codes; Multi rate; Orthogonal frequency division multiplexing (OFDM); Signal to noise ratio (SNR); VLSI

Indexed keywords

ALGORITHMS; BLOCK CODES; CODES (SYMBOLS); COMMUNICATION CHANNELS (INFORMATION THEORY); DECODING; ERROR CORRECTION; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; SIGNAL ENCODING; SIGNAL INTERFERENCE; SIGNAL TO NOISE RATIO; VLSI CIRCUITS;

BLOCK-ERROR RATE; CHANNEL ENCODING; CYCLE ELIMINATION; FORWARD ERROR CORRECTION (FEC); LOW-DENSITY PARITY-CHECK (LDPC) CODES;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33645807178     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.862074     Document Type: Article

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