Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 5194-5197

  Darabiha, Ahmad ^a   Carusone, Anthony Chan ^a   Kschischang, Frank R ^a   Rogers Sr , Edward S ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-PARALLEL; CHECK NODES; CMOS PROCESS; INTERCONNECT WIRES; LDPC DECODER; LOW DENSITY PARITY CHECK; PLACEMENT ALGORITHM; WIRE LENGTH;

WIRE;

DECODING;

EID: 67649112194     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465805     Document Type: Conference Paper

References (14)

1. R. G. Gallager, Low-Density Parity-Check Codes. Cambridge, MA: MIT press, 1963.
2. C. Berrou and A. Glavieux, "Near optimum error correcting coding: Turbo codes," IEEE Trans. on Communications, vol. 44, pp. 1261-1271, Oct 1996.
3. B. Vasic and I. B. Djordjevic, "Low-density parity check codes for long-haul optical communication systems," IEEE Photonics Technology Letters, vol. 14, pp. 1208-1210, Aug 2002.
4. T. Mittelholzer, A. Dholakia, and E. Eleftheriou, "Reduced- complexity decoding of low density parity check codes for generalized partial response channels," IEEE Trans. on Magnetics, vol. 37, no. 2, pp. 721-728, March 2001.
5. IEEE 802.3 10GBase-T Study Group Meeting, World Wide Web, http: //www.ieee802.org/3/10GBT/public/jul04/rao-1-0704.pdf, July 2004.
6. European Telecommunication Standards Institue, World Wide Web, http: //www.dvb.org/documents/white-papers/wp06.DVB-S2.final.pdf.
7. A. J. Blanksby and C. J. Howland, "A 690-mw 1-Gb/s 1024-b, rate-1/2 low-density parity-check decoder," IEEE Journal of Solid-State Circuits, vol. 37, no. 3, March 2002.
8. F. R. Kschischang, B. J. Frey, and H. A. Loeliger, "Factor graphs and the sum-product algorithm," IEEE Trans. on Information Theory, vol. 47, pp. 498-519, Feb 2001.
9. E. Boutillon, J. Castura, and F. R. Kschischang, "Decoder-first code design," in Proceedings of Turbo Codes, Brest, France, 2000, pp. 459-462.
10. M. M. Mansour and N. R. Shanbhag, "High-throughput LDPC decoders," Trans. on VLSI Systems, vol. 11, no. 6, Dec 2003.
11. T. Zhang and K. K. Parhi, "Joint code and decoder design for implementation-oriented (3, k)-regular LDPC codes," in IEEE Asilomar Conference, Nov 2001, pp. 1232-1236.
12. M. Mohiyuddin, A. Prakash, A. Aziz, and W. Wolf, "Synthesizing interconnect-efficient low density parity check codes," in Design Automation Conference, June 2004, pp. 488-491.
13. J. Thorpe, "Design of LDPC graphs for hardware implementation," in International Symposium on Information Technology, Lausanne, Switzerland, July 2002.
14. I. Djurdjevic, J. Xu, K. Abdel-Ghaffar, and S. Lin, "A class of lowdensity parity-check codes constructed based on Reed-Solomon codes with two information symbols," IEEE Comm. Letters, vol. 7, no. 7, July 2003.