High-throughput LDPC decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 6, 2003, Pages 976-996

  Mansour, Mohammad M ^a   Shanbhag, Naresh R ^b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Low density parity check (LDPC) codes; Ramanujan graphs; Soft input soft output (SISO) decoder; Turbo decoding algorithm; VLSI decoder architectures

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DECODING; DESIGN FOR TESTABILITY; TURBO CODES;

LOW DENSITY PARITY CHECK DECODERS; RAMANUJAN GRAPHS; SOF INPUT SOFT OUTPUT MESSAGE; TURBO DECODING ALGORITHM;

VLSI CIRCUITS;

EID: 0742286682     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.817545     Document Type: Article

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