Architecture and evaluation of an asynchronous array of simple processors

Journal of Signal Processing Systems

Volumn 53, Issue 3, 2008, Pages 243-259

  Yu, Zhiyi ^a   Meeuwsen, Michael J ^a   Apperson, Ryan W ^a   Sattari, Omar ^a   Lai, Michael A ^a   Webb, Jeremy W ^a   Work, Eric W ^a   Mohsenin, Tinoosh ^a   Baas, Bevan M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Array processor; Chip multi processor; Digital signal processing; DSP; GALS; Globally asynchronous locally synchronous; Many core; Multi core; Programmable DSP

Indexed keywords

ARRAY PROCESSOR; CHIP MULTI-PROCESSOR; DIGITAL SIGNAL PROCESSING; DSP; GALS; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; MANY-CORE; MULTI-CORE; PROGRAMMABLE DSP;

CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSORS; EFFICIENCY; INTERCONNECTION NETWORKS; NETWORK PROTOCOLS; SENSOR NETWORKS;

ENERGY EFFICIENCY;

EID: 53649089271     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-008-0162-1     Document Type: Article

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