A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 3, 2004, Pages 484-493

  Maharatna, Koushik ^a   Grass, Eckhard ^b   Jagdhold, Ulrich ^b  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

^b IHP   (Germany)

Author keywords

Discrete Fourier transforms; Integrated circuits; Wireless LAN

Indexed keywords

BROADBAND NETWORKS; CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; DISCRETE FOURIER TRANSFORMS; ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING; WIRELESS TELECOMMUNICATION SYSTEMS;

COMPLEX MULTIPLICATION; DIGITAL MULTIPLIER;

LOCAL AREA NETWORKS;

EID: 1542500848     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.822776     Document Type: Article

References (26)

1. Draft Supplement to Standard [for] Information Technology-Telecommunications and Information Exchange Between Systems - Local and Metropolitan Area Networks-Specific Requirements - Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High Speed Physical Layer in the 5 GHz Band, IEEE P802.11a/D7.0.
2. T. Xanthopoulos and A. P. Chandrakasan, "A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity," IEEE J. Solid-State Circuits, vol. 34, pp. 693-703, May 1999.
3. E. Grass, K. Tittelbach, U. Jagdhold, A. Troya, G. Lippert, O. Krueger, J. Lehmann, K. Maharatna, N. Fiebig, K. Dombrowski, R. Kraemer, and P. Maehoenen, "On the single chip implementation of a hiperlan/2 and IEEE802.11a capable modem," IEEE Pers. Commun., vol. 8, pp. 48-57, Dec. 2001.
4. K. Maharatna, E. Grass, and U. Jagdhold, "A novel 64-point FFT/IFFT processor for IEEE 802.11a standard," in Proc. ICASSP'03, vol. II, pp. II-321-II-324.
5. C. Chen and L. Wang, "A new efficient systolic architecture for the 2-D discrete Fourier transform," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 6, ch. 732, 1992, pp. 689-692.
6. M. Ghouse, "2D grid architectures for the DFT and the 2D DFT," J. VLSI Signal Process., vol. 5, pp. 57-74, 1993.
7. H. Lim and E. Swartzlander, "A systolic array for 2-D DFT and 2-D DCT," in Proc. Int. Conf. Application Specific Array Processors, 1994, pp. 123-131.
8. N. Zhang, X. Zhang, and C. Zhang, "Two kinds of array architecture for FFT processor," in Proc. Int. Conf. Signal Processing, vol. 2, ch. 355, 1990, pp. 1161-1162.
9. J. Muller and D. Trystram, "Perfect shuffle VLSI implementation: Applications to sorting and FFT computation," in Proc. CONPAR '88, pp. 197-204.
10. B. Gold and T. Bially, "Parallelism in fast Fourier transform hardware," IEEE Trans. Audio Electroacous., vol. 21, pp. 5-16, Feb. 1973.
11. E. Bidet, D. Castelain, and P. Senn, "A fast single-chip implementation of 8192 complex point FFT," IEEE J. Solid-State Circuits, vol. 30, pp. 300-305, Mar. 1995.
12. E. Swartzlander, V. Jain, and H. Hikawaka, "A radix-8 wafer scale FFT processor," J. VLSI Signal Processing, vol. 4, pp. 165-176, 1992.
13. H. Yeh, "Highly pipelined VLSI architecture for computation of fast fourier transforms," Proc. SPIE, vol. 2027, pp. 112-121, 1993.
14. V. Szwarc and L. Desormeaux, "A chip set for pipeline and parallel pipeline FFT architectures," J. VLSI Signal Processing, vol. 8, pp. 253-265, 1994.
15. C. W. Hui, T. J. Ding, and J. V. McCanny, "A 64-point Fourier transform chip for video motion compensation using phase correlation," IEEE J. Solid-State Circuits, vol. 31, pp. 1751-1761, Nov. 1996.
16. R. Bhatia, M. Furuta, and J. Ponce, "A quasi radix-16 FFT VLSI processor," in Proc. IEEE Acoustics, Speech, and Signal Processing (ICASSP), Apr. 1991, p.
17. J. O'Brien, J. Mather, and B. Holland, "A 200 MIPS single-chip 1K FFT processor," in IEEE Solid-State Circuits Conf. (ISCCC) Dig. Tech. Papers, Feb. 1989, pp. 166-167, 327.
18. A. M. Despain, "Very fast Fourier transform algorithms hardware for implementation," IEEE Trans. Comput., vol. C-28, no. 5, pp. 333-341, 1979.
19. K. Maharatna, E. Grass, and U. Jagdhold, "A low-power 64-point FFT/IFFT architecture for wireless broadband communication," in Proc. 5th Int. OFDM Workshop, Hamburg, Germany, Sept. 2000, p. 36.
20. Xilinx Product Specification, High-Performance 64-Point Complex FFT/IFFT V1.0.5 [Online]. Available: http://www.xilinx.com/ipcenter
21. Altera Megafunction Technical Brief ISS High-Performance 64-Point FFT/IFFT [Online]. Available: http://www.spinnaker.co.jp/jp/datasheet/tb_fft_1_V002.pdf
22. Product Design Data Sheet, FFT-1024 Complex 1024-Points FFT/IFFT Processor. Icomm Technologies Inc. [Online]. Available: www.icommtech.com/Products/FFT-64.PDF
23. M3 Architecture Specification Rev. 1.3: Functional Specification, Technische Universität, Dresden, Germany, 1999.
24. J. V. McCanny, D. Trainor, Y. Hu, and T. J. Ding, Rapid design of complex DSP cores. [Online]. Available: http://www.esscirc.org/papers-97/102.pdf
25. T. Chen and L. Zhu, "An expandable column FFT architecture using circuit switching network," J. VLSI Signal Process., vol. 6, no. 3, pp. 243-257, Dec. 1993.
26. T. Chen, G. Sunanda, and J. Jin, "COBRA: A 100-MOPS single-chip programmable and expandable FFT," IEEE Trans. VLSI, vol. 7, pp. 174-182, June 1999.