CASCADE - Configurable and scalable DSP environment

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2002, Pages

  Lin, Tay Jyi ^a   Jen, Chein Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); COMPUTER HARDWARE; COMPUTER SOFTWARE; EMBEDDED SYSTEMS; SYNCHRONIZATION;

AUTO-GENERATED SOFTWARE DRIVER; MEMORY MANAGEMENT UNITS; OFF-THE-SHELF COMPONENTS;

DIGITAL SIGNAL PROCESSING;

EID: 0036296191     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. DSP-based architectures for mobile communications: Past, present and future
2. Scalable performance scheduling for hardware-software co-synthesis
3. Hardware-software co-synthesis for digital systems
4. Xtensa: A configurable and extensible processor
5. Embedded computer architecture and automation
6. Data stream generation for concurrent computation in VLSI signal processors
7. Low power data format converter design using semi-static register allocation
8. Design of data format converters using two-dimensional register allocation
9. Effective compiler support for predicated execution using the hyperblock
10. Formal equivalence checking of folded architectures
11. Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis
12. Bitwidth analysis with application to silicon compilation
13. Retiming synchronous circuitry