A 1.5GHz third generation Itanium® 2 processor

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 706-709

  Stinson, Jason ^a   Rusu, Stefan ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Design methodology; On die cache; Processor; Reliability; Test

Indexed keywords

BANDWIDTH; CACHE MEMORY; DIELECTRIC MATERIALS; PARALLEL PROCESSING SYSTEMS; TRANSISTORS;

EXPLICITLY PARALLEL INSTRUCTION COMPUTING (EPIC);

MICROPROCESSOR CHIPS;

EID: 0042134652     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/776008.776011     Document Type: Conference Paper

References (4)

1. S. Tyagi, et al, - "A 130nm generation logic technology featuring 70nm transistors, dual Vt transistors and 6 layers of Cu interconnects", IEDM Tech. Digest, Dec. 2000
2. S. Thompson, et al, - "An enhanced 130nm generation logic technology featuring 60nm transistors optimized for high performance and low power", IEDM Tech. Digest, Dec. 2001
3. S. Rusu, G. Singer - "The first IA-64 microprocessor," IEEE J. Solid-State Circuits, Nov. 2000, pp 1539-1544
4. S. Naffziger, G. Hammond - "The implementation of the next-generation 64b Itanium® microprocessor", ISSCC Dig. Tech. Papers, Feb. 2002, pp 344-472