A parallel programmable energy-efficient architecture for computationally-intensive DSP systems

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2003, Pages 2185-2192

  Baas, Bevan M ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA DENSITY; BASEBAND PROCESSORS; FABRICATION TECHNOLOGY; WORKLOADS;

ARCHITECTURAL DESIGN; DATA FLOW ANALYSIS; DATA STORAGE EQUIPMENT; ENERGY EFFICIENCY; FIR FILTERS; LOCAL AREA NETWORKS; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); PARAMETER ESTIMATION; PROGRAM PROCESSORS;

PARALLEL PROCESSING SYSTEMS;

EID: 4143066042     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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