Scalable sub-10ps skew global clock distribution for a 90nm multi-GHz IA microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Bindal, Niraj ^a   Kelly, Timothy ^a   Velastegui, Nicholas ^a   Wong, Keng L ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; DELAY CIRCUITS; ELECTRIC CURRENTS; ELECTRIC INVERTERS; INTEGRATED CIRCUIT LAYOUT; JITTER; MICROPROCESSOR CHIPS; TIMING DEVICES;

CLOCK SKEW; DELAY MATCHING; INVERTER DELAY; SKEW GLOBAL CLOCK DISTRIBUTION;

PIPELINE PROCESSING SYSTEMS;

EID: 0037630786     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. N. Kurd, et al., "Multi-GHz Clocking Scheme for Intel® Pentium® 4 Microprocessor," ISSCC Digest of Technical Papers, 2001.
2. N. Bindal, E. Friedman, "Challenges in Clock Distribution Networks" invited papers, International Symposium on Physical Design, 1999.