Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2002-January, Issue , 2002, Pages 283-293

  Kozyrakis, Christoforos ^a   Patterson, David ^b  

^a STANFORD UNIVERSITY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Clocks; Design optimization; Digital signal processing chips; Energy consumption; Frequency; Manuals; Prototypes; Reduced instruction set computing; Vector processors; VLIW

Indexed keywords

ARRAY PROCESSING; BENCHMARKING; CLOCKS; CODES (SYMBOLS); COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; DIGITAL SIGNAL PROCESSORS; DYNAMIC RANDOM ACCESS STORAGE; ENERGY UTILIZATION; MICROPROCESSOR CHIPS; PROGRAM COMPILERS; PROGRAM PROCESSORS; REDUCED INSTRUCTION SET COMPUTING; SIGNAL PROCESSING; VECTORS;

DESIGN OPTIMIZATION; DIGITAL SIGNAL PROCESSING CHIPS; FREQUENCY; MANUALS; PROTOTYPES; VECTOR PROCESSORS; VLIW;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 84948978169     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2002.1176257     Document Type: Conference Paper

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