A 600-MHz VLIW DSP

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 11, 2002, Pages 1532-1544

  Agarwala, Sanjive ^a   Anderson, Timothy ^a   Hill, Anthony ^a   Ales, Michael D ^a   Damodaran, Raguram ^a   Wiley, Paul ^a   Mullinnix, Steven ^a   Leach, Jerald ^a   Lell, Anthony ^a   Gill, Michael ^a   Rajagopal, Arjun ^a   Chachad, Abhijeet ^a   Agarwala, Manisha ^a   Apostol, John ^a   Krishnan, Manjeri ^a   Bui, Duc ^a   An, Quang ^a   Nagaraj, N S ^a   Wolf, Tod ^a   Elappuparackal, Tony Thomas ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

Cache; Digital signal processor (DSP); DMA; Signal integrity; Turbo decoder; Viterbi decoder; VLIW

Indexed keywords

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COPPER; DECODING; INTEGRATED CIRCUIT MANUFACTURE; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; TRANSISTORS; TURBO CODES;

DIGITAL SIGNAL PROCESSOR; SEMI CUSTOM STANDARD CELL; TURBO DECODER; VITERBI DECODER;

DIGITAL SIGNAL PROCESSING;

EID: 0036858553     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.803954     Document Type: Article

References (8)

1. S. Agarwala, P. Koeppen, T. Anderson, A. Hill, M. ALes, R. Damodaran, L. Nardini, P. Wiley, S. Mullinnix, J. Leach, A. Lell, M. Gill, J. Golston, D. Hoyle, A. Rajagopal, A. Chachad, M. Agarwala, R. Castille, N. Common, J. Apostol, H. Mahmood, M. Krishnan, D. Bui, Q. An, P. Groves, N. NS, L. Nguyen, and R. Simar, "A 600 MHz VLIW DSP," in Proc. ISSCC Dig. Tech. Papers, Feb. 2002, pp. 56-57.
2. TMS320C6000 CPU and Instruction Set Reference Guide, Texas Instruments, 2000.
3. A. Gatherer and E. Auslander, The Application of Programmable DSP's in Mobile Communications. New York: Wiley, 2001, ch. 3.
4. S. Agarwala, C. Fuoco, T. Anderson, D. Comisky, and C. Mobley, "A multi-level memory system architecture for high performance DSP applications," in Proc. ICCD, Austin, TX, Oct. 2000.
5. D. Comisky, S. Agarwala, and C. Fuoco, "A scalable high-performance DMA architecture for DSP applications," in Proc. ICCD, Austin, TX, Oct. 2000.
6. T. Rost and B. Hunter, "Building in reliability," presented at the Proc. CICC Tutorial, San Diego, CA, 1999.
7. G. La Rosa, S. Rauch, and F. Guarin, "New phenomena in device reliability physics of advanced CMOS submicron technologies," in Proc. IRPS, San Jose, CA, 2000.
8. A. E. Ruehli, "Equivalent circuit models for three-dimensional conductor systems," IEEE Trans. Microwave Theory Tech., MTT-22, pp. 216-221, Mar. 1974.