Tile size selection for low-power tile-based architectures

Proceedings of the 3rd Conference on Computing Frontiers 2006, CF '06

Volumn 2006, Issue , 2006, Pages 83-93

  Oliver, John ^a   Rao, Ravishankar ^a   Brown, Michael ^b   Mankin, Jennifer ^b   Franklin, Diana ^b   Chong, Frederic T ^c   Akella, Venkatesh ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b CALIFORNIA POLYTECHNIC STATE UNIVERSITY   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Media; Multi core processors; Processors

Indexed keywords

GRANULARITY INDICATOR (GI); MULTICORE PROCESSORS; SYNCHROSCALAR TILE ARCHITECTURE; TILE BASED PROCESSORS;

ALGORITHMS; COMPUTATIONAL METHODS; ELECTRIC POWER UTILIZATION; PROGRAM PROCESSORS; SOFTWARE DESIGN;

SOFTWARE ARCHITECTURE;

EID: 34247356639     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1128022.1128036     Document Type: Conference Paper

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