Fabrication and characterization of fin SONOS flash memory with separated double-gate structure

Solid-State Electronics

Volumn 52, Issue 10, 2008, Pages 1498-1504

  Yun, Jang Gn ^a   Kim, Yoon ^a   Park, Il Han ^a   Lee, Jung Hoon ^a   Kang, Sangwoo ^a   Lee, Dong Hua ^a   Cho, Seongjae ^a   Kim, Doo Hyun ^a   Lee, Gil Sung ^a   Sim, Won Bo ^a   Son, Younghwan ^a   Shin, Hyungcheol ^a   Lee, Jong Duk ^a   Park, Byung Gook ^a  

^a Seoul National University   (South Korea)

Author keywords

3 Dimensional structure; 4 Bit cell operation; Fin SONOS flash memory; Separated double gate

Indexed keywords

FINS (HEAT EXCHANGE); OPTICAL DESIGN; SILICON;

3-DIMENSIONAL; 3-DIMENSIONAL STRUCTURE; 4-BIT/CELL OPERATION; ARRAY STRUCTURES; DOUBLE GATES; FABRICATED DEVICES; FIN SONOS FLASH MEMORY; MULTI-BIT; OPERATION SCHEMES; SEPARATED DOUBLE-GATE; SONOS FLASH MEMORY;

FLASH MEMORY;

EID: 50849128793     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2008.06.021     Document Type: Article

References (27)

1. Bez R, Cappelletti P. Flash memory and beyond. In: VLSI technical digest; 2005. p. 84-7.
2. Hwang C.G. Nanotechnology enables a new memory growth model. Proc IEEE 91 (2003) 1765-1771
3. Pavan P., Bez R., Olivo P., and Zanoni E. Flash memory cells - an overview. Proc IEEE 85 (1999) 1248-1271
4. Oh CW, Kim SH, Kim NY, Choi YL, Lee KH, Kim BS, et al. A 4-bit double SONOS memory (DSM) with 4 storage nodes per cell for ultimate multi-bit operation. In: VLSI technical digest; 2006. p. 50-1.
5. Lee Y.K., Sim J.S., Sung S.K., Lee C.J., Kim T.H., Lee J.D., et al. Multilevel vertical-channel SONOS nonvolatile memory on SOI. IEEE Electron Dev Lett 23 (2002) 664-666
6. Wu J.Y., Lee M.H., Hsu T.H., Kuo M.C., Lung H.L., Liu R., et al. An asymmetric two-side program with one-side read (ATPOR) device for multibit per cell MLC nitride-trapping flash memories. IEEE Trans Electron Dev 52 (2005) 2648-2653
7. Liu Z., Lee C., Narayanan V., Pei G., and Kan E.C. A novel quad source/drain metal nanocrystal memory device for multibit-per-cell storage. IEEE Electron Dev Lett 24 (2003) 345-347
8. Salvo B., Gerardi C., Schaijk R., Lombardo S.A., Corso D., Plantamura C., et al. Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS). IEEE Trans Dev Mater Reliab 4 (2004) 377-389
9. Park BG, Lee YK, Choi BY, Park DG. Nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) structure and its applications. In: 2004 Asia-Pacific workshop on fundamentals and applications of advanced semiconductor devices; 2004. p. 684-97.
10. Eitan B., Pavan P., Bloom I., Aloni E., Frommer A., and Finzi D. NROM: a novel localized trapping, 2-bit nonvolatile memory cell. IEEE Electron Dev Lett 21 (2000) 543-545
11. Eitan B, Cohen G, Shappir A, Lusky E, Givant A, Janai M, et al. 4-bit per cell NROM reliability. In: IEDM technical digest; 2005. p. 539-42.
12. Sugizaki T, Kobayashi M, Ishidao M, Minakata H, Yamaguchi M, Tamura Y, et al. Novel multi-bit SONOS type flash memory using a high-k charge trapping layer. In: VLSI technical digest; 2003. p. 27-8.
13. Tiwari S, Rana F, Chan K, Hanafi H, Chan W, Buchanan D. Volatile and non-volatile memories in silicon with nano-crystal storage. In: IEDM technical digest; 1995. p. 521-4.
14. Chien H.C., Kao C.H., Chang J.W., and Tsai T.K. Two-bit SONOS type flash using a band engineering in the nitride layer. Microelectron Eng 80 (2005) 256-259
15. Lee C., Hou T.H., and Kan E.C.C. Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate. IEEE Trans Electron Dev 52 (2005) 2697-2702
16. Crupi I., Corso D., Ammendola G., Lombardo S., Gerardi C., Salvo B., et al. Peculiar aspects of nanocrystal memory cells: data and extrapolations. IEEE Trans Nanotechnol 2 (2003) 319-323
17. Lee Y.K., Kim T.H., Lee S.H., Lee J.D., and Park B.G. Twin-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory by inverted sidewall patterning (TSM-ISP). IEEE Trans Nanotechnol 2 (2003) 246-252
18. Fukuda M., Nakanishi T., and Nara Y. New nonvolatile memory with charge-trapping sidewall. IEEE Electron Dev Lett 24 (2003) 490-492
19. Endoh T., Kinoshita K., Tanigami T., Wada Y., Sato K., Yamada K., et al. Novel ultrahigh-density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell. IEEE Trans Electron Dev 50 (2003) 945-951
20. Yuen K.H., Man T.Y., Chan A.C.K., and Chan M. A 2-bit MONOS nonvolatile memory cell based on asymmetric double gate MOSFET structure. IEEE Electron Dev Lett 24 (2003) 518-520
21. Choi B.Y., Park B.G., Lee J.D., Shin H., Lee Y.K., Bai K.H., et al. Reliable 2-bit/cell NVM technology using twin SONOS memory transistor. Electron Lett 41 (2005) 1086-1087
22. Yun JG, Kim Y, Park IH, Cho SJ, Lee JH, Kim DH, et al. Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation. In: IEEE nanotechnology materials and devices conference 2006; 2006. p. 214-5.
23. Kim NY, Oh CW, Hong SI, Kim SH, Choi YL, Bae HJ, et al. A study on the 8-bit operational double SONOS memory (DSM) cell transistor. In: 2007 Silicon nanoelectronics workshop; 2007. p. 179-80.
24. Yun JG, Kim Y, Park IH, Cho S, Lee JH, Lee GS, et al. Study of programming characteristics of 4-bit SONOS flash memory using 3-dimensional transient simulation. In: Second international conference on memory technology and design; 2007. p. 81-4.
25. Lee J.H. Two-bit/cell NFGM devices for high-density NOR flash memory. J Semiconductor Technol Sci 8 (2008) 11-20
26. Cheo J.D., Yeo K.H., Ahn Y.J., Lee J.J., Lee S.H., Choi B.Y., et al. Low voltage program/erase characteristics of Si nanocrystal memory with damascene gate FinFET on bulk Si wafer. J Semiconductor Technol Sci 6 (2006) 68-73
27. Kim E., Kim K., Son D., Kim J., Lee K., Won S., et al. Nonvolatile memory characteristics of double-stacked Si nanocluster floating gate transistor. J Semiconductor Technol Sci 8 (2008) 27-31