New nonvolatile memory with charge-trapping sidewall

IEEE Electron Device Letters

Volumn 24, Issue 7, 2003, Pages 490-492

  Fukuda, Masatoshi ^a   Nakanishi, Toshiro ^a   Nara, Yasuo ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Charge trapping sidewall; Junction edge; MOSFET technology; Nonvolatile memory

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); NONVOLATILE STORAGE; OPTIMIZATION; SILICON NITRIDE; THRESHOLD VOLTAGE;

CHARGE TRAPPING SIDEWALLS; JUNCTION EDGE;

MOSFET DEVICES;

EID: 0041385786     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.815002     Document Type: Letter

References (13)

1. 7 erase/write cycles," IEEE Trans. Electron Devices, vol. 40, pp. 2011-2017, Nov. 1993.
2. M. H. White, D. A. Adams, and J. Bu, "On the go with SONOS," IEEE Circuits Devices Mag., vol. 16, pp. 22-32, July 2000.
3. ([Online] Available: http://public.itrs.net/2001) ITRS Roadmap
4. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: a novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Lett., vol. 21, pp. 543-545, Nov. 2000.
5. Y. K. Lee, J. S. Sim, S. K. Sung, C. J. Lee, T. H. Kim, J. D. Lee, B. G. Park, D. H. Lee, and Y. W. Kim, "Multilevel vertical-channel SONOS nonvolatile memory on SOI," IEEE Electron Device Lett., vol. 23, pp. 664-666, Nov. 2002.
6. S. T. Kang, S. W. Park, Y. S. Park, B. Y. Seo, K. W. Kho, S. G. Kim, J. W. Han, S. B. Yoon, and C. H. Chung, "A study of SONOS nonvolatile memory cell controlled structurally by localizing charge-trapping layer," in Proc. IEEE Nonvolatile Semiconductor Memory Workshop, 2003, pp. 39-41.
7. S. Baba, A. Kita, and J. Ueda, "Mechanism of hot carrier induced degradation in MOSFETs," in IEDM Tech. Dig., 1986, pp. 734-737.
8. T. Tsuchiya, T. Kobayashi, and S. Nakajima, "Hot-carrier-injected oxide region and hot-electron trapping as the main cause in Si nMOSFET degradation," IEEE Trans. Electron Devices, vol. ED-34, pp. 386-391, Feb. 1987.
9. Y. Kamigaki, S. Minami, and H. Kato, "A new portrayal of electron and hole traps in amorphous silicon nitride," J. Appl. Phys., vol. 68, pp. 2211-2215, Sep. 1990.
10. E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, "Characterization of channel hot electron injection by the subthreshold slope of NROMTM device," IEEE Electron Device Lett., vol. 22, pp. 556-558, Nov. 2001.
11. H. Lee, S. Chang, J. Lee, and H. Shin, "Characteristics of MOSFET with nonoverlapped source-drain to gate," IEICE Trans. Electron., vol. E85-C, pp. 1079-1085, May 2002.
12. G. Ingrosso, L. Selmi, and E. Sangiorgi, "Monte Carlo simulation of program and erase charge distributions in NROMTM devices," in Proc. European Solid State Device Res. Conf., 2002, pp. 187-190.
13. E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, "Electrons retention model for localized charge in oxide-nitride-oxide (ONO) dielectric," IEEE Electron Device Lett., vol. 23, pp. 556-558, Sep. 2002.