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Volumn 52, Issue 12, 2005, Pages 2648-2653

An asymmetric two-side program with one-side read (ATPOR) device for multibit per cell MLC nitride-trapping flash memories

Author keywords

2 bit cell; 3 bit cell; Multilevel cell (MLC); Nitride trapping device; Second bit effect

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CHARGE; ELECTRIC CURRENT MEASUREMENT; THRESHOLD VOLTAGE; VOLTAGE MEASUREMENT;

EID: 29244437579     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.859665     Document Type: Article
Times cited : (4)

References (11)
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  • 2
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  • 3
    • 10644240078 scopus 로고    scopus 로고
    • "Investigation of maximum current sensing window for two-side operation, 4-bit/cell MLC nitride-trapping nonvolatile Flash memories"
    • Dec
    • T. H. Hsu, M. H. Lee, J. Y. Wu, H. L. Lung, R. Liu, and C.-Y. Lu, "Investigation of maximum current sensing window for two-side operation, 4-bit/cell MLC nitride-trapping nonvolatile Flash memories," IEEE Electron Device Lett., vol. 25, no. 12, pp. 795-797, Dec. 2004.
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    • "Modeling for the second bit effect of a nitride-based trapping storage Flash EEPROM cell under two-bit operation"
    • Feb
    • Y. W. Chang, T. C. Lu, S. Pan, and C. Y. Lu, "Modeling for the second bit effect of a nitride-based trapping storage Flash EEPROM cell under two-bit operation," IEEE Electron Device Lett., vol. 25, no. 2, pp. 95-97, Feb. 2004.
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  • 9
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    • T. Wang, W. J. Tsai, S. H. Gu, C. T. Chan, C. C. Yeh, N. K. Zous, T. C. Lu, S. Pan, and C.-Y. Lu, "Reliability models of data retention and read disturb in 2-bit nitride storage Flash memory cells (Invited)," in IEDM Tech. Dig., 2003, pp. 7.4.1-7.4.4.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.