Investigation of 4-bit SONOS nonvolatile memory using 3-dimensional numerical simulation

2006 IEEE Nanotechnology Materials and Devices Conference, NMDC

Volumn 1, Issue , 2006, Pages 214-215

  Yun, J G ^a   Kim, Y ^a   Park, I H ^a   Cho, S J ^a   Lee, J H ^a   Kim, D H ^a   Lee, G S ^a   Song, J Y ^a   Lee, J D ^a   Park, B G ^a  

^a Seoul National University   (South Korea)

Author keywords

3 dimensional numerical simulation; 3 dimensional structure; 4 bit SONOS device; VTH window

Indexed keywords

COMPUTER SIMULATION; NANOTECHNOLOGY;

3-DIMENSIONAL; 3-DIMENSIONAL NUMERICAL SIMULATION; 3-DIMENSIONAL STRUCTURE; 4-BIT SONOS DEVICE; CHANNEL LENGTHS; NON-VOLATILE MEMORIES; NUMERICAL SIMULATIONS; STORED CHARGE; VTH WINDOW;

TECHNOLOGY;

EID: 50249095652     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NMDC.2006.4388845     Document Type: Conference Paper

References (4)

1. C. W. Oh, S. H. Kim, N. Y. Kim, Y. L. Choi, K. H. Lee, B. S. Kim, N. M. Cho, S. B. Kim, D. W. Kim, D. Q. Park, and B. I. Ryu, "A 4-Bit Double SONOS Memory (DSM) with 4 Storage Nodes per Coll for Ultimate Multi-Bit Operation," Symp. on VLSI technology, pp. 50-51, 2006.
2. Y. K. Lee, J. S. Sim, S. K. Sung, C. J. Lee, T. H. Kim, J. D. Lee, B. G. Park, D. H. Lee, and Y. W. Kim, "Multilevel Vertical-Channel SONOS Nonvolatile Memory on SOI," IEEE Electron Device Lett., pp. 664-666, 2002.
3. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Lett., pp. 543-545,2000.
4. Y. K. Lee, T. H. Kim, S. H. Lee, J. D. Lee, and G. B. Park, "Twin-Bit Silicon-Oxide-Nitridc-Oxide-Silicon (SONOS) Memory by Inverted Sidewall Patterning (TSM-ISP)," IEEE Trans. Nanoteohnol., pp. 246-252, 2003.