Reliable 2-bit/cell NVM technology using twin SONOS memory transistor

Electronics Letters

Volumn 41, Issue 19, 2005, Pages 1086-1087

  Choi, B Y ^a   Park, B G ^a   Lee, J D ^a   Shin, H ^a   Lee, Y K ^b   Bai, K H ^b   Kim, D D ^b   Kim, D W ^b   Lee, C H ^b   Park, D ^b  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LINES; SHAPE MEMORY EFFECT;

GATE LENGTH; NON-VOLATILE-MEMORY (NVM) APPLICATIONS; SIDEWALL SPACER PROCESSES; TWIN SONOS MEMORY (TSM) TRANSISTORS;

FIELD EFFECT TRANSISTORS;

EID: 25444455362     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20052070     Document Type: Article

References (5)

1. White, M.H., Yang, Y., Purwar, A., and French, M.L.: 'A low voltage SONOS nonvolatile semiconductor memory technology', IEEE Trans. Compon. Packag. Manuf. Technol., 1997, 20, (2), pp. 190-195
2. Eitan, B., Pavan, P., Bloom, I., Efraim, A., Frommer, A., and Finzi, D.: 'NROM: a novel localized trapping, 2-bit nonvolatile memory cell', IEEE Electron Device Lett., 2000, 21, (11), pp. 543-545
3. Lusky, E., Shacham-Diamand, Y., Mitenberg, G., Shappir, A., Bloom, I., and Eitan, B.: 'Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices', IEEE Trans. Electron Devices, 2004, 51, (3), pp. 444-451
4. Lee, Y.K., Song, K.W., Hyun, J.W., Lee, J.D., Park, B.-G., Kang, S.T., Choe, J.D., Han, S.Y., Han, J.N., Lee, S.W., Kwon, O.I., Chung, C., Park, D., and Kim, K.: 'Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process', IEEE Electron Device Lett., 2004, 25, (5), pp. 317-319
5. Fukuda, M., Nakanishi, T., and Nara, Y.: 'Scaled 2 bit/cell SONOS type nonvolatile memory technology for sub-90 nm embedded application using SiN sidewall trapping structure'. Tech. Dig. Int. Electron Devices Mtg, Washington, DC, USA, December 2003, pp. 909-912