Testing of hard faults in simultaneous multithreaded processors

Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

Volumn , Issue , 2004, Pages 95-100

  Weglarz, Eric F ^a   Saluja, Kewal K ^a   Mak, T M ^b  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC IMPLEMENTATION VERIFICATION ARCHITECTURE (DIVA); ONLINE TESTING; POWER CONSUMPTION; VARIABLE FREQUENCY;

CLOCKS; COMPUTATIONAL COMPLEXITY; COMPUTER OPERATING SYSTEMS; COMPUTER SOFTWARE; ERROR DETECTION; FREQUENCIES; METALLIZING; ONLINE SYSTEMS; PERSONAL COMPUTERS;

INTEGRATED CIRCUITS;

EID: 10444240260     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2004.1319665     Document Type: Conference Paper

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