Design for testability features of the SUN Microsystems Niagara2 CMP/CMT SPARC chip

Proceedings - International Test Conference

Volumn , Issue , 2007, Pages

  Molyneaux, Robert ^a   Ziaja, Tom ^a   Kim, Hong ^a   Aryani, Shahryar ^a   Hwang, Sungbae ^a   Hsieh, Alex ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; MICROPROCESSOR CHIPS; SOFTWARE ARCHITECTURE;

BITMAPPING ARCHITECTURE; HYBRID FLOP DESIGN; MULTITHREADED SERVERS;

DESIGN FOR TESTABILITY;

EID: 39749187671     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2007.4437561     Document Type: Conference Paper

References (6)