Gate-stack analysis for 45-nm CMOS devices from an RF perspective

IEEE Transactions on Electron Devices

Volumn 53, Issue 4, 2006, Pages 925-929

  Nuttinck, Sebastien ^a   Curatola, Gilberto ^a   Widdershoven, Frans ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

45 nm; CMOS; Contact resistance; Gate stack; Noise; RF

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); SEMICONDUCTING SILICON COMPOUNDS; SPURIOUS SIGNAL NOISE;

GATE WORK FUNCTIONS; MULTILAYER GATE STACKS; SILICIDED GATES;

MOS DEVICES;

EID: 33645736422     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.870878     Document Type: Article

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