-
1
-
-
0032277985
-
An effective gate resistance model for CMOS RF and noise modeling
-
Dec
-
X. Jin, J.-J. Ou, C.-H. Chen, W. Liu, M. Deen, P. Gray, and C. Hu, "An effective gate resistance model for CMOS RF and noise modeling," in IEDM Tech. Dig., Dec. 1998, pp. 961-964.
-
(1998)
IEDM Tech. Dig
, pp. 961-964
-
-
Jin, X.1
Ou, J.-J.2
Chen, C.-H.3
Liu, W.4
Deen, M.5
Gray, P.6
Hu, C.7
-
2
-
-
0035249128
-
High frequency characterization of gate resistance in RF MOSFETs
-
Feb
-
Y. Cheng and M. Matloubian, "High frequency characterization of gate resistance in RF MOSFETs," IEEE Electron Device Lett., vol. 22, no. 2, pp. 98-100, Feb. 2001.
-
(2001)
IEEE Electron Device Lett
, vol.22
, Issue.2
, pp. 98-100
-
-
Cheng, Y.1
Matloubian, M.2
-
3
-
-
2442536561
-
-
Hoboken, NJ: Wiley, May
-
T. A. Fjeldly, T. Ytterdal, and Y. Cheng, Device Modeling for Analog and RF CMOS Circuit Design. Hoboken, NJ: Wiley, May 2003.
-
(2003)
Device Modeling for Analog and RF CMOS Circuit Design
-
-
Fjeldly, T.A.1
Ytterdal, T.2
Cheng, Y.3
-
4
-
-
0028747636
-
A relaxation time approach to model the non-quasi-static transient effects in MOSFETs
-
Dec
-
M. Chan, K. Hui, R. Neff, C. Hu, and P. K. Ko, "A relaxation time approach to model the non-quasi-static transient effects in MOSFETs," in IEDM Tech. Dig., Dec. 1994, pp. 169-172.
-
(1994)
IEDM Tech. Dig
, pp. 169-172
-
-
Chan, M.1
Hui, K.2
Neff, R.3
Hu, C.4
Ko, P.K.5
-
5
-
-
21644442219
-
RF CMOS gate resistance and noise characterization
-
Oct
-
J. Tao, A. Rezvani, and P. Findley, "RF CMOS gate resistance and noise characterization," in Proc. IEEE Int. Conf. Solid-State and Integr.-Circuit Technol., Oct. 2004, vol. 1, pp. 159-162.
-
(2004)
Proc. IEEE Int. Conf. Solid-State and Integr.-Circuit Technol
, vol.1
, pp. 159-162
-
-
Tao, J.1
Rezvani, A.2
Findley, P.3
-
6
-
-
0242468144
-
A simple four-port parasitic deembedding methodology for high-frequency scattering parameter and noise characterization of SiGe HBTs
-
Nov
-
Q. Q. Liang, J. D. Cressler, G. Niu, Y. Lu, G. Freeman, D. C. Ahlgren, R. M. Malladi, K. Newton, and D. L. Harame, "A simple four-port parasitic deembedding methodology for high-frequency scattering parameter and noise characterization of SiGe HBTs," IEEE Trans. Microw. Theory Tech., vol. 51, no. 11, pp. 2165-2174, Nov. 2003.
-
(2003)
IEEE Trans. Microw. Theory Tech
, vol.51
, Issue.11
, pp. 2165-2174
-
-
Liang, Q.Q.1
Cressler, J.D.2
Niu, G.3
Lu, Y.4
Freeman, G.5
Ahlgren, D.C.6
Malladi, R.M.7
Newton, K.8
Harame, D.L.9
-
7
-
-
0036687560
-
Small-signal and temperature noise model for MOSFETs
-
Aug
-
A. Pascht, M. Gröing, D. Wiegner, and M. Berroth, "Small-signal and temperature noise model for MOSFETs," IEEE Trans. Microw. Theory Tech., vol. 50, no. 8, pp. 1927-1934, Aug. 2002.
-
(2002)
IEEE Trans. Microw. Theory Tech
, vol.50
, Issue.8
, pp. 1927-1934
-
-
Pascht, A.1
Gröing, M.2
Wiegner, D.3
Berroth, M.4
-
9
-
-
33750593702
-
-
Berkeley, CA: BSIM Research Group, Univ. California, Mar
-
X. Xi, M. Dunga, J. He, W. Liu, K. M. Cao, X. Jin, J. J. Ou, M. Chan, A. M. Niknejad, and C. Hu, BSIM4 Manual. Berkeley, CA: BSIM Research Group, Univ. California, Mar. 2004.
-
(2004)
BSIM4 Manual
-
-
Xi, X.1
Dunga, M.2
He, J.3
Liu, W.4
Cao, K.M.5
Jin, X.6
Ou, J.J.7
Chan, M.8
Niknejad, A.M.9
Hu, C.10
-
11
-
-
0024170834
-
+ polysilicon in a dual-gate CMOS process
-
+ polysilicon in a dual-gate CMOS process," in IEDM Tech. Dig., 1988, pp. 238-241.
-
(1988)
IEDM Tech. Dig
, pp. 238-241
-
-
Wong, C.1
Sun, J.2
Taur, Y.3
Oh, C.4
Angelucci, R.5
Davari, B.6
-
12
-
-
0028756974
-
Determination of ultra-thin gate oxide thickness for CMOS structures using quantum effects
-
R. Rios and N. Arora, "Determination of ultra-thin gate oxide thickness for CMOS structures using quantum effects," in IEDM Tech. Dig., 1994, pp. 613-616.
-
(1994)
IEDM Tech. Dig
, pp. 613-616
-
-
Rios, R.1
Arora, N.2
-
13
-
-
0015490526
-
Characterization and measurement of the base and emitter resistances of bipolar transistors
-
Dec
-
W. Sansen and R. Meyer, "Characterization and measurement of the base and emitter resistances of bipolar transistors," IEEE J. Solid-State Circuits, vol. SSC-7, no. 6, pp. 492-498, Dec. 1972.
-
(1972)
IEEE J. Solid-State Circuits
, vol.SSC-7
, Issue.6
, pp. 492-498
-
-
Sansen, W.1
Meyer, R.2
|