On-FPGA communication architectures and design factors

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 161-168

  Mak, Terrence S T ^a   Sedcole, Pete ^a   Cheung, Peter Y K ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION ARCHITECTURES; COMMUNICATION BAND WIDTH; COMPUTING POWERS; DESIGN FACTORS; EMBEDDED COMPONENTS; EMBEDDED MEMORIES; EMBEDDED PROCESSORS; FIELD PROGRAMMABLE LOGIC (FPL); INTERNATIONAL CONFERENCES; INTERPROCESSOR COMMUNICATIONS; IP CORES; LIMITING FACTORS; ON-CHIP COMMUNICATION ARCHITECTURES (OOCA); PERFORMANCE METRICS; PROGRAMMABLE SYSTEM-ON-CHIP (PSOC); QUALITATIVE FACTORS; RAPID SYSTEM PROTOTYPING; RECENT DEVELOPMENT; SYSTEM PERFORMANCES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ARCHITECTURE; COMMUNICATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; SURVEYS;

ARCHITECTURAL DESIGN;

EID: 46249096381     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311209     Document Type: Conference Paper

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